ST STM32L4+ Series Reference Manual page 540

Flexible static memory controller (FSMC)
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 CNTB4EN: Counter Bank 4 enable
This bit enables the chip select counter for PSRAM/NOR Bank 4.
0: Counter disabled for Bank 4
1: Counter enabled for Bank 4
Bit 18 CNTB3EN: Counter Bank 3 enable
This bit enables the chip select counter for PSRAM/NOR Bank 3.
0: Counter disabled for Bank 3.
1: Counter enabled for Bank 3
Bit 17 CNTB2EN: Counter Bank 2 enable
This bit enables the chip select counter for PSRAM/NOR Bank 2.
0: Counter disabled for Bank 2
1: Counter enabled for Bank 2
Bit 16 CNTB1EN: Counter Bank 1 enable
This bit enables the chip select counter for PSRAM/NOR Bank 1.
0: Counter disabled for Bank 1
1: Counter enabled for Bank 1
Bits 15:0 CSCOUNT[15:0]: Chip select counter.
These bits are written by software to define the maximum chip select low pulse duration. It is
expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous
accesses.
The counter is disabled if the programmed value is 0.
18.8 NAND Flash controller
The FMC generates the appropriate signal timings to drive the following types of device:
•
8- and 16-bit NAND Flash memories
The NAND bank is configured through dedicated registers
programmable memory parameters include access timings (shown in
configuration.
Parameter
Memory setup
time
Memory wait
540/2301
Table 113. Programmable NAND Flash access parameters
Function
Number of clock cycles (HCLK)
required to set up the address
before the command assertion
Minimum duration (in HCLK clock
cycles) of the command assertion
RM0432 Rev 6
(Section 18.8.7). The
Table
Access mode Unit
AHB clock cycle
Read/Write
(HCLK)
AHB clock cycle
Read/Write
(HCLK)
RM0432
113) and ECC
Min. Max.
1 255
2 255