ST STM32L4+ Series Reference Manual page 565

RM0432
When reading the status registers of the devices in Dual-quad mode, twice as many bytes
must be read compared to the same read in Regular mode: if each device gives eight valid
bits after the instruction for fetching the status register, then the OCTOSPI must be
configured with a data length of 2 bytes (16 bits), and the OCTOSPI receives one byte from
each device.
If each device gives a status of 16 bits, then the OCTOSPI must be configured to read
4 bytes to get all the status bits of both devices in Dual-quad mode. The least-significant
byte of the result (in the data register) is the least-significant byte of device A status register.
The next byte is the least-significant byte of device B status register. Then, the third byte of
the data register is the device A second byte. The forth byte is the device B second byte (if
devices have 16-bit status registers).
An even number of bytes must always be accessed in Dual-quad mode. For this reason,
bit 0 of the DL[31:0] field in OCTOSPI_DLR is stuck at 1 when DQM = 1.
In Dual-quad mode, the behavior of device A interface signals is basically the same as in
Normal mode. Device B interface signals have exactly the same waveforms as Device A
ones during the instruction, address, alternate-byte, and dummy-cycles phases. In other
words, each device always receives the same instruction and the same address.
Then, during the data phase, the AIOx and the BIOx buses both transfer data in parallel, but
the data that is sent to (or received from) device A is distinct than the one from device B.
19.4.5 HyperBus mode
In HyperBus mode, the OCTOSPI can communicate with the external device using the
HyperBus protocol.
The HyperBus uses 11 to 12 pins depending on the operating voltage:
•
IO[7:0] as bidirectional data bus
•
RWDS for read and write data strobe and latency insertion (mapped on DQS pin)
•
nCS
•
CLK
The HyperBus does not require any command specification nor any alternate bytes. As a
consequence, a separate register set is used to define the timing of the transaction.
The HyperBus frame is composed of two phases:
•
Command/address phase
•
Data phase
The nCS falls before the start of a transaction and rises again after each transaction
finishes.
RM0432 Rev 6
Octo-SPI interface (OCTOSPI)
565/2301
603