ST STM32L4+ Series Reference Manual page 223

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Bit 13 EXT_SMPS_RDY: External SMPS ready

Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices.

Bits 12:9 Reserved, must be kept at reset value.

Bit 8 SBF: Standby flag

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 WUF5: Wakeup flag 5

Bit 3 WUF4: Wakeup flag 4

Bit 2 WUF3: Wakeup flag 3

Bit 1 WUF2: Wakeup flag 2

Bit 0 WUF1: Wakeup flag 1

Power status register 2 (PWR_SR2)

Address offset: 0x14

Reset value: 0x0000 0000 (This register is partially reset when exiting Standby/Shutdown

PVMO4 PVMO3 PVMO2 PVMO1 PVDO

This bit informs the state of regulator transition from Range 1 to Range 2

0: Internal regulator not ready in Range 2, the external SMPS cannot be connected

1: Internal regulator ready in Range 2, the external SMPS can be connected

This bit is set by hardware when the device enters the Standby mode and is cleared by

setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the

system reset.

0: The device did not enter the Standby mode

1: The device entered the Standby mode

This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by

writing '1' in the CWUF5 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by

writing '1' in the CWUF4 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by

writing '1' in the CWUF3 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by

writing '1' in the CWUF2 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by

writing '1' in the CWUF1 bit of the PWR_SCR register.

RM0432 Rev 6

Power control (PWR)

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