ST STM32L4+ Series Reference Manual page 390

Direct memory access controller (DMA)
Bit 8 CGIF3: global interrupt flag clear for channel 3
Bit 7 CTEIF2: transfer error flag clear for channel 2
Bit 6 CHTIF2: half transfer flag clear for channel 2
Bit 5 CTCIF2: transfer complete flag clear for channel 2
Bit 4 CGIF2: global interrupt flag clear for channel 2
Bit 3 CTEIF1: transfer error flag clear for channel 1
Bit 2 CHTIF1: half transfer flag clear for channel 1
Bit 1 CTCIF1: transfer complete flag clear for channel 1
Bit 0 CGIF1: global interrupt flag clear for channel 1
11.6.3 DMA channel x configuration register (DMA_CCRx)
Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR
are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
MEM2
Res. PL[1:0]
MEM
rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM: memory-to-memory mode
0: disabled
1: enabled
Note: this bit is set and cleared by software.
Bits 13:12 PL[1:0]: priority level
00: low
01: medium
10: high
11: very high
Note: this field is set and cleared by software.
390/2301
27 26 25
Res. Res. Res. Res.
11 10 9
MSIZE[1:0] PSIZE[1:0]
rw rw rw
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
RM0432 Rev 6
24 23 22 21
Res. Res. Res.
8 7 6 5
MINC PINC CIRC
rw rw rw rw
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
DIR TEIE HTIE TCIE
rw rw rw rw
RM0432
16
Res.
0
EN
rw