ST STM32L4+ Series Reference Manual page 520

Flexible static memory controller (FSMC)
Bit number
7
6
5:4
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
520/2301
Table 104. FMC_BCRx bitfields (mode D) (continued)
Bit name
Reserved 0x1
FACCEN Set according to memory support
MWID As needed
MTYP As needed
MUXEN 0x0
MBKEN 0x1
Table 105. FMC_BTRx bitfields (mode D)
Bit name
Duration of the data hold phase (DATAHLD HCLK cycles for read
DATAHLD
accesses).
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for read
DATAST
accesses.
Duration of the middle phase of the read access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 1.
Table 106. FMC_BWTRx bitfields (mode D)
Bit name
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
DATAHLD
accesses).
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
DATAST Duration of the second access phase (DATAST HCLK cycles).
Duration of the middle phase of the write access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 1.
RM0432 Rev 6
Value to set
Value to set
Value to set
RM0432