ST STM32L4+ Series Reference Manual page 541

RM0432
Table 113. Programmable NAND Flash access parameters (continued)
Parameter
Memory hold
Memory
databus high-Z
18.8.1 External memory interface signals
The following tables list the signals that are typically used to interface NAND Flash memory.
Note: The prefix "N" identifies the signals which are active low.
8-bit NAND Flash memory
FMC signal name
NOE(= NRE)
NWAIT/INT
Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.
Function
Number of clock cycles (HCLK)
during which the address must be
held (as well as the data if a write
access is performed) after the
command de-assertion
Number of clock cycles (HCLK)
during which the data bus is kept
in high-Z state after a write
access has started
Table 114. 8-bit NAND Flash
I/O
A[17] O
A[16] O
D[7:0] I/O
NCE O
O
NWE O
I
Flexible static memory controller (FSMC)
Access mode
Read/Write
Write
NAND Flash address latch enable (ALE) signal
NAND Flash command latch enable (CLE) signal
8-bit multiplexed, bidirectional address/data bus
Chip select
Output enable (memory signal name: read enable, NRE)
Write enable
NAND Flash ready/busy input signal to the FMC
RM0432 Rev 6
Unit
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
Function
Min. Max.
1 254
1 255
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