ST STM32L4+ Series Reference Manual page 448

Chrom-ART Accelerator controller (DMA2D)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 LO[15:0]: Line offset
13.5.18 DMA2D number of line register (DMA2D_NLR)
Address offset: 0x0044
Reset value: 0x0000 0000
31 30 29
Res. Res.
rw
15 14 13
rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:16 PL[13:0]: Pixel per lines
Bits 15:0 NL[15:0]: Number of lines
13.5.19 DMA2D line watermark register (DMA2D_LWR)
Address offset: 0x0048
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
448/2301
The line offset used for the output expressed in pixel when the LOM bit is reset and in
byte when the LOM bit is set.
When expressed in pixels, only LO[13:0] is considered, LO[15:14] are ignored.
This value is used for the address generation. It is added at the end of each line to
determine the starting address of the next line.
These bits can only be written when data transfers are disabled. Once data transfer has
started, they become read-only.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Number of pixels per lines of the area to be transferred. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
If any of the input image format is 4-bit per pixel, pixel per lines must be even.
Number of lines of the area to be transferred. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
PL[13:0]
rw rw rw
8 7 6
NL[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
LW[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
RM0432
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
rw rw