ST STM32L4+ Series Reference Manual page 907

RM0432
29.8.6 LTDC shadow reload configuration register (LTDC_SRCR)
This register allows to reload either immediately or during the vertical blanking period, the
shadow registers values to the active registers. The shadow registers are all Layer1 and
Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 VBR: vertical blanking reload
This bit is set by software and cleared only by hardware after reload (it cannot be cleared
through register write once it is set).
0: no effect
1: The shadow registers are reloaded during the vertical blanking period (at the beginning of
the first line after the active display area).
Bit 0 IMR: immediate reload
This bit is set by software and cleared only by hardware after reload.
0: no effect
1: The shadow registers are reloaded immediately.
Note: The shadow registers read back the active values. Until the reload has been done, the 'old'
value is read.
29.8.7 LTDC background color configuration register (LTDC_BCCR)
This register defines the background color (RGB888).
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
BCGREEN[7:0]
rw rw rw rw
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
rw rw rw rw
RM0432 Rev 6
LCD-TFT display controller (LTDC)
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Res. Res. Res. Res.
23 22 21 20
BCRED[7:0]
rw rw rw rw
7 6 5 4
BCBLUE[7:0]
rw rw rw rw
19 18 17 16
Res. Res. Res. Res.
3 2 1
Res. Res. VBR IMR
rw
19 18 17 16
rw rw rw
3 2 1
rw rw rw
907/2301
0
rw
rw
0
rw
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