ST STM32L4+ Series Reference Manual page 1039

RM0432
Bit 15 Reserved
Bits 14:11 IDF: PLL Input Division Factor
Bits 10: 9 Reserved
Bits 8:2 NDIV: PLL Loop Division Factor
Bit 1 Reserved
Bit 0 PLLEN: PLL Enable
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
This field configures the PLL Input Division Factor:
000: PLL input divided by 1.
001: PLL input divided by 1.
010: PLL input divided by 2.
011: PLL input divided by 3.
100: PLL input divided by 4.
101: PLL input divided by 5.
110: PLL input divided by 6.
111: PLL input divided by 7.
This field configures the PLL Loop Division Factor:
0 to 9: Reserved.
10 to 125: Allowed loop division factor values.
126 to 127: Reserved.
This bit enables the D-PHY PLL:
0: PLL disable.
1: PLL enable.
RM0432 Rev 6 1039/2301
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