ST STM32L4+ Series Reference Manual page 848

Digital filter for sigma delta modulators (DFSDM)
filter must perform two input samplings from channel y to empty DFSDM_CHyDATINR
register. This mode is used together with 32-bit CPU/DMA access to
DFSDM_CHyDATINR register to load two samples per write operation.
3. Dual mode (DATPACK[1:0]=2):
Two samples are written into DFSDM_CHyDATINR register. The data INDAT0[15:0] is
for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is
automatically copied INDAT0[15:0] of the following (y+1) channel data register
DFSDM_CH[y+1]DATINR). The digital filters must perform two samplings - one from
channel y and one from channel (y+1) - in order to empty DFSDM_CHyDATINR
registers.
Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y =
0, 2, 4, 6). If odd channel (y = 1, 3, 5, 7) is set to Dual mode then both INDAT0[15:0]
and INDAT1[15:0] parts are write protected for this channel. If even channel is set to
Dual mode then the following odd channel must be set into Standard mode
(DATPACK[1:0]=0) for correct cooperation with even channels.
See Figure 197
samples to channels.
Figure 197. DFSDM_CHyDATINR registers operation modes and assignment
Standard mode
31
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
The write into DFSDM_CHyDATINR register to load one or two samples must be performed
after the selected input channel (channel y) is enabled for data collection (starting
conversion for channel y). Otherwise written data are lost for next processing.
For example: for single conversion and interleaved mode, do not start writing pair of data
samples into DFSDM_CHyDATINR before the single conversion is started (any data
present in the DFSDM_CHyDATINR before starting a conversion is discarded).
28.4.7 Channel selection
There are 8 multiplexed channels which can be selected for conversion using the injected
channel group and/or using the regular channel.
The injected channel group is a selection of any or all of the 8 channels. JCHG[7:0] in the
DFSDM_FLTxJCHGR register selects the channels of the injected group, where JCHG[y]=1
means that channel y is selected.
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for DFSDM_CHyDATINR registers data modes and assignments of data
16 15 0 31
Ch0 (sample 0) Ch0 (sample 1) Ch0 (sample 0)
Ch1 (sample 0) Ch1 (sample 1) Ch1 (sample 0)
Ch2 (sample 0) Ch2 (sample 1) Ch2 (sample 0)
Ch3 (sample 0) Ch3 (sample 1) Ch3 (sample 0)
Ch4 (sample 0) Ch4 (sample 1) Ch4 (sample 0)
Ch5 (sample 0) Ch5 (sample 1) Ch5 (sample 0)
Ch6 (sample 0) Ch6 (sample 1) Ch6 (sample 0)
Ch7 (sample 0) Ch7 (sample 1) Ch7 (sample 0)
RM0432 Rev 6
Interleaved mode
16 15 0
Ch1 (sample 0) Ch0 (sample 0)
Ch3 (sample 0) Ch2 (sample 0)
Ch5 (sample 0) Ch4 (sample 0)
Ch7 (sample 0) Ch6 (sample 0)
Dual mode
31 16 15
Unused Ch1 (sample 0)
Unused Ch3 (sample 0)
Unused Ch5 (sample 0)
Unused Ch7 (sample 0)
RM0432
0
y = 0
y = 1
y = 2
y = 3
y = 4
y = 5
y = 6
y = 7
MS35354V3