ST STM32L4+ Series Reference Manual page 966

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
If the PLL gets unlocked, the PLLUIF bit of the DSI_WISR is set. If the PLLUIE bit of the
DSI_WIER register is set, an interrupt is generated.
The DSI PLL setting can be changed only when the PLL is disabled.
30.12.5 Regulator control
The DSI regulator providing the 1.2 V is controlled through the DSI Wrapper.
The regulator is enabled setting the REGEN bit of the DSI_WRPCR register.
Once the regulator is ready, the RRIF bit of the DSI_WISR register is set. If the RRIE bit of
the DSI_WIER register is set, an interrupt is generated.
The regulator status (ready or not) can be monitored with the RRS flag in the DSI_WISR
register.
Note that the D-PHY has no separated Power ON control bit. The power ON/OFF of the D-
PHY is done directly enabling the 1.2 V regulator.
When the 1.2 V regulator is disabled, the 3.3 V part of the D-PHY is automatically powered
OFF.
966/2301 RM0432 Rev 6
RM0432