ST STM32L4+ Series Reference Manual page 941

RM0432
8 bit
pwdata(0)
R1[4:0]
pwdata(1)
R3[4:0]
pwdata(2)
R5[4:0]
pwdata(3)
R7[4:0]
8 bit
G1
pwdata(0)
[3:0]
R4
pwdata(1)
[3:0]
B6
pwdata(2)
[3:0]
G9
pwdata(3)
[3:0]
8 bit
R2
pwdata(0)
[2:0] [2:0]
R6
pwdata(1)
[2:0] [2:0]
R10 G10
pwdata(2)
[2:0] [2:0]
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
Figure 212. 16 bpp APB pixel to byte organization
[31 ...................... 0]
8 bit
G0[2:0]
G1[5:3]
G3[5:3] G2[2:0]
G5[5:3] G4[2:0]
G6[2:0]
G7[5:3]
Figure 213. 12 bpp APB pixel to byte organization
[31 ...................... 0]
8 bit
B1 B0
[3:0] [3:0]
G4 G3
[3:0] [3:0]
R7 R6
[3:0] [3:0]
B9 B8
[3:0] [3:0]
Figure 214. 8 bpp APB pixel to byte organization
[31 ...................... 0]
8 bit
G2 B2 R1 G1
[1:0] [2:0] [2:0]
G6 B6 R5 G5
[1:0] [2:0] [2:0]
B10 R9 G9
[1:0] [2:0] [2:0]
8 bit
B0[4:0] R0[4:0] G0[5:3]
B2[4:0] R2[4:0] G2[5:3]
B4[4:0] R4[4:0] G4[5:3]
B6[4:0] R6[4:0] G6[5:3]
8 bit
R1 R0 G0
[3:0] [3:0] [3:0]
B3 B2 R3
[3:0] [3:0] [3:0]
G6 G5 B5
[3:0] [3:0] [3:0]
R9 R8 G8
[3:0] [3:0] [3:0]
8 bit
B1 R0 G0
[1:0] [2:0] [2:0]
B5 R4 G4
[1:0] [2:0] [2:0]
B9 R8 G8
[1:0] [2:0] [2:0]
RM0432 Rev 6
8 bit
Write_mem
Command
G1[2:0] B1[4:0]
G3[2:0] B3[4:0]
G5[2:0] B5[4:0]
8 bit
Write_mem
Command
R2 G2
[3:0] [3:0]
B4 R5
[3:0] [3:0]
G7 B7
[3:0] [3:0]
8 bit
B0 Write_mem
[1:0] Command
B4 R3 G3 B3
[1:0] [2:0] [2:0] [1:0]
B8 R7 G7 B7
[1:0] [2:0] [2:0] [1:0]
Pixel
16 bpp
R0
[4:0]
G0
[5:0]
B0
[4:0]
MSv35863V1
Pixel
12 bpp
R0
[3:0]
G0
[3:0]
B0
[3:0]
MSv35864V1
Pixel
8 bpp
R0
[2:0]
G0
[2:0]
B0
[1:0]
MSv35865V1
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