ST STM32L4+ Series Reference Manual page 927

RM0432
standard procedure to estimate the minimum lane rate and the minimum number of lanes
that support a specific display device.
The basic assumptions for estimates are:
•
clock lane frequency is 250 MHz, resulting in a bandwidth of 500 Mbps for each data
lane;
•
the display should be capable of buffering the pixel data at the speed at which it is
delivered in the DSI link;
•
no significant control traffic is present on the link when the pixel data is being
transmitted.
30.4.3 System level architecture
Figure 205
LTDC
The different parts have the following functions:
•
The DSI Wrapper ensures the interfacing between the LTDC and the DSI Host kernel.
It can adapt the color mode, the signal polarity and manages the Tearing Effect (TE)
management for automatic frame buffer update in Adapted Command mode. The DSI
Wrapper also control the DSI Regulator, the DSI PLL and specific functions of the
MIPI
•
The LTDC interface captures the data and control signals from the LTDC and conveys
them to a FIFO for video control signals and another one for the pixel data. This data is
then used to build one of the following:
–
–
•
The Register Bank is accessible through a standard AMBA-APB slave interface,
providing access to the DSI Host registers for configuration and control. There is also a
fully programmable interrupt generator to inform the system about certain events.
•
The PHY Interface Control is responsible for managing the D-PHY interface. It
acknowledges the current operation and enables Low-Power transmission/reception or
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
shows the architecture of the DSI Host
Figure 205. DSI Host architecture
Ctrl
RGB
DSI
RGB
Wrapper
APB
APB
®
D-PHY.
Video packets, when in Video mode (see
The memory_write_start and memory_write_continue DCS commands, when in
Adapted Command mode (see
DSI Host
LTDC
I/F
Packet D-PHY
Handler
APB to
Generic
Register Error
Bank Management
Section
Section 30.6)
RM0432 Rev 6
Regulator
PLL
PPI
I/F
D-PHY
30.5)
DATAP1
DATAN1
DATAP0
DATAN0
CLKP
CLKN
MSv37300V1
927/2301
1044