ST STM32L4+ Series Reference Manual page 313

RM0432
Bits 6:2 Reserved, must be kept at reset value
Bit 1 HSI48RDY: HSI48 clock ready flag
Bit 0 HSI48ON: HSI48 clock enable
6.4.32 Peripherals independent clock configuration register (RCC_CCIPR2)
Address: 0x9C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31 30 29
Res. Res. Res.
15 14 13
SDMMC DSISE
Res. Res.
SEL
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 OSPISEL: Octospi clock source selection
Set and reset by software.
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:16 PLLSAI2DIVR: division factor for LTDC clock
Set and reset by software to control the frequency of LTDC clock.
These bits can only be written when PLLSAI2 is disabled.
LTDC clock frequency = f(PLLSAI2_R) / PLLSAI2DIVR with 2 <= PLLSAI2DIVR <= 16
Bit 15 Reserved, must be kept at reset value.
Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is
enabled by software by setting HSI48ON.
0: HSI48 oscillator not ready
1: HSI48 oscillator ready
Set and cleared by software.
Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.
0: HSI48 oscillator OFF
1: HSI48 oscillator ON
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. SAI2SEL[2:0]
L
rw rw
00: system clock selected as OctoSPI kernel clock
01: MSI clock selected as OctoSPI kernel clock
10: PLL48M1CLK clock selected as OctoSPI kernel clock
11: reserved
00: PLLSAI2DIVR = /2
01: PLLSAI2DIVR = /4
10: PLLSAI2DIVR = /8
11: PLLSAI2DIVR = /16
24 23 22
Res. Res. Res. OSPISEL[1:0]
8 7 6
SAI1SEL[2:0]
rw
RM0432 Rev 6
Reset and clock control (RCC)
21 20 19 18
Res. Res.
rw
5 4 3 2
ADFSDMSEL[1: DFSD
0] MSEL
rw rw
17 16
PLLSAI2DIVR[1:
0]
rw
1 0
I2C4SEL[1:0]
rw
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