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RM0432
Bit 2 MSIRDYC: MSI ready interrupt clear
Bit 1 LSERDYC: LSE ready interrupt clear
Bit 0 LSIRDYC: LSI ready interrupt clear
6.4.10
AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x28
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
15
14
13
CRCR
Res.
Res.
Res.
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 GFXMMURST: GFXMMU reset
Set and cleared by software
0: No effect
1: Reset GFXMMU
Bit 17 DMA2DRST: DMA2D reset
Set and cleared by software
0: No effect
1: Reset DMA2D
Bit 16 TSCRST: Touch Sensing Controller reset
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF cleared
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
ST
rw
Set and cleared by software.
0: No effect
1: Reset TSC
Set and cleared by software.
0: No effect
1: Reset CRC
24
23
22
Res.
Res.
Res.
8
7
6
FLASH
Res.
Res.
RST
rw
RM0432 Rev 6
Reset and clock control (RCC)
21
20
19
18
GFXMM
Res.
Res.
Res.
URST
rw
5
4
3
2
DMAMU
Res.
Res.
Res.
X1RST
rw
17
16
DMA2
TSCR
DRST
ST
rw
rw
1
0
DMA2
DMA1
RST
RST
rw
rw
277/2301
320
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