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DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
Bit 8 LPVSAE: Low-Power Vertical Sync Active Enable
Bits 7: 2 Reserved, must be kept at reset value
Bits 1: 0 VMT: video mode Type
30.15.12 DSI Host video Packet Configuration Register (DSI_VPCR)
Address offset: 0x003C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Bits 31: 14 Reserved, must be kept at reset value
Bits 13: 0 VPSIZE: video Packet Size
30.15.13 DSI Host video Chunks Configuration Register (DSI_VCCR)
Address offset: 0x0040
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
992/2301
This bit enables to return to Low-Power inside the Vertical Sync time (VSA) period when
timing allows.
0: Return to Low-Power inside the VSA is disabled.
1: Return to Low-Power inside the VSA is enabled
This field configures the video mode transmission type :
00: Non-Burst with sync pulses.
01: Non-Burst with sync events.
1x: Burst mode
28
27
26
25
Res.
Res.
Res.
12
11
10
9
This field configures the number of pixels in a single video packet.
For 18-bit not loosely packed data types, this number must be a multiple of 4.
For YCbCr data types, it must be a multiple of 2 as described in the DSI specification.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
24
23
22
Res.
Res.
Res.
8
7
6
VPSIZE[13:0]
rw
24
23
22
Res.
Res.
Res.
8
7
6
NUMC[12:0]
rw
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
RM0432
17
16
Res.
Res.
1
0
17
16
Res.
Res.
1
0
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