ST STM32L4+ Series Reference Manual page 249

RM0432
can use the USB SOF signal, the LSE or an external signal to automatically and quickly
adjust the oscillator frequency on-fly. It is disabled as soon as the system enters Stop or
Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its default
frequency which is subject to manufacturing process variations.
For more details on how to configure and use the CRS peripheral please refer to
Clock recovery system
The HSI48RDY flag in the Clock recovery RC register (RCC_CRRCR) indicates whether the
HSI48 RC oscillator is stable or not. At startup, the HSI48 RC oscillator output clock is not
released until this bit is set by hardware.
The HSI48 can be switched on and off using the HSI48ON bit in the Clock recovery RC
register (RCC_CRRCR).
6.2.5 PLL
The device embeds 3 PLLs: PLL, PLLSAI1, PLLSAI2. Each PLL provides up to three
independent outputs. The internal PLLs can be used to multiply the HSI16, HSE or MSI
output clock frequency. The PLLs input frequency must be between 4 and 16 MHz. The
selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a
clock frequency in the requested input range. Refer to
STM32L4Rxxx and STM32L4Sxxx
(RCC_PLLCFGR).
The PLLs configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0 in
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN in
configuration register
An interrupt can be generated when the PLL is ready, if enabled in the
enable register
The same procedure is applied for changing the configuration of the PLLSAI1 or PLLSAI2:
1. Disable the PLLSAI1/PLLSAI2 by setting PLLSAI1ON/PLLSAI2ON to 0 in
register
2. Wait until PLLSAI1RDY/PLLSAI2RDY is cleared. The PLLSAI1/PLLSAI2 is now fully
stopped.
3. Change the desired parameter.
4. Enable the PLLSAI1/PLLSAI2 again by setting PLLSAI1ON/PLLSAI2ON to 1.
5. Enable the desired PLL outputs by configuring PLLSAI1PEN/PLLSAI2PEN,
PLLSAI1QEN/PLLSAI2QEN, PLLSAI1REN/PLLSAI2REN in
register (RCC_PLLSAI1CFGR)
(RCC_PLLSAI2CFGR).
The PLL output frequency must not exceed 120 MHz.
(CRS).
(RCC_PLLCFGR).
(RCC_CIER).
(RCC_CR).
RM0432 Rev 6
Figure 16: Clock tree for
devicesand PLL configuration register
Clock control register
and PLLSAI2 configuration register
Reset and clock control (RCC)
(RCC_CR).
Clock interrupt
Clock control
PLLSAI1 configuration
Section 7:
PLL
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