ST STM32L4+ Series Reference Manual page 426

Chrom-ART Accelerator controller (DMA2D)
13.3.11 DMA2D transactions
DMA2D transactions consist of a sequence of a given number of data transfers. The
number of data and the width can be programmed by software.
Each DMA2D data transfer is composed of up to 4 steps:
1. Data loading from the memory location pointed by the DMA2D_FGMAR register and
pixel format conversion as defined in DMA2D_FGCR.
2. Data loading from a memory location pointed by the DMA2D_BGMAR register and
pixel format conversion as defined in DMA2D_BGCR.
3. Blending of all retrieved pixels according to the alpha channels resulting of the PFC
operation on alpha values.
4. Pixel format conversion of the resulting pixels according to the DMA2D_OCR register
and programming of the data to the memory location addressed through the
DMA2D_OMAR register.
13.3.12 DMA2D configuration
Both source and destination data transfers can target peripherals and memories in the
whole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and
0xFFFF FFFF.
The DMA2D can operate in any of the four following modes selected through MODE[2:0]
bits of the DMA2D_CR register:
•
Register-to-memory
•
Memory-to-memory
•
Memory-to-memory with PFC
•
Memory-to-memory with PFC and blending
•
Memory-to-memory with PFC, blending and fixed FG color
•
Memory-to-memory with PFC, blending and fixed BG color
Register-to-memory
The register-to-memory mode is used to fill a user defined area with a predefined color.
The color format is set in the DMA2D_OPFCCR.
The DMA2D does not perform any data fetching from any source. It just writes the color
defined in the DMA2D_OCOLR register to the area located at the address pointed by the
DMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR.
Memory-to-memory
In memory-to-memory mode, the DMA2D does not perform any graphical data
transformation. The foreground input FIFO acts as a buffer and the data are transferred
from the source memory location defined in DMA2D_FGMAR to the destination memory
location pointed by DMA2D_OMAR.
The color mode programmed in the CM[3:0] bits of the DMA2D_FGPFCCR register defines
the number of bits per pixel for both input and output.
The size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR
registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the
destination.
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