ST STM32L4+ Series Reference Manual page 905

RM0432
29.8.4 LTDC total width configuration register (LTDC_TWCR)
This register defines the accumulated number of horizontal synchronization, back porch,
active and front porch pixels minus 1 (HSYNC width + HBP + active width + HFP - 1) and
the accumulated number of vertical synchronization, back porch lines, active and front lines
minus 1 (VSYNC height + BVBP + active height + VFP - 1). Refer to
Section 29.5: LTDC programmable parameters
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 TOTALW[11:0]: total width (in units of pixel clock period)
These bits defines the accumulated total width which includes the horizontal synchronization,
horizontal back porch, active width and horizontal front porch pixels minus 1.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 TOTALH[10:0]: total height (in units of horizontal scan line)
These bits defines the accumulated height which includes the vertical synchronization,
vertical back porch, the active height and vertical front porch height lines minus 1.
29.8.5 LTDC global control register (LTDC_GCR)
This register defines the global configuration of the LCD-TFT controller.
Address offset: 0x18
Reset value: 0x0000 2220
31 30 29
HSPOL VSPOL DEPOL PCPOL
rw rw rw
15 14 13
Res. DRW[2:0]
r r
27 26 25
rw rw rw
11 10 9
Res.
rw rw
28 27 26 25
Res. Res. Res.
rw
12 11 10 9
Res. DGW[2:0]
r r r
for an example of configuration.
24 23 22 21
TOTALW[11:0]
rw rw rw rw
8 7 6 5
TOTALH[10:0]
rw rw rw rw
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. DBW[2:0]
r r r
RM0432 Rev 6
LCD-TFT display controller (LTDC)
Figure 200
20 19 18
rw rw rw
4 3 2
rw rw rw
20 19 18
Res. Res. Res.
4 3 2
Res. Res.
r
and
17 16
rw rw
1 0
rw rw
17 16
Res. DEN
rw
1 0
Res. LTDCEN
rw
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