ST STM32L4+ Series Reference Manual page 519

RM0432
A[25:0]
NADV
NBL[x:0]
NEx
NOE
NWE
Data bus
The differences with mode 1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Bit number
31:24
23:22
21
20
19
18:16
15
14
13
12
11
10
9
8
Figure 58. Mode D write access waveforms
NBLSET ADDSET HCLK cycles
HCLK
cycles
Table 104. FMC_BCRx bitfields (mode D)
Bit name
Reserved 0x000
NBLSET[1:0] As needed
WFDIS As needed
CCLKEN As needed
CBURSTRW 0x0 (no effect in Asynchronous mode)
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x1
WAITEN 0x0 (no effect in Asynchronous mode)
WREN As needed
WAITCFG Don't care
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
RM0432 Rev 6
Flexible static memory controller (FSMC)
Memory transaction
Data driven by controller
ADDHLD DATAST HCLK cycles
HCLK cycles
Value to set
DATAHLD +1
HCLK cycles
MSv41684V1
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