ST STM32L4+ Series Reference Manual page 1009

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Bit 2 PSSC: PHY Stop State Clock lane

Bit 1 PD: PHY Direction

Bit 0 Reserved

30.15.41 DSI Host Interrupt & Status Register 0 (DSI_ISR0)

Address offset: 0x00BC

Reset value: 0x0000 0000

Bits 31: 21 Reserved, must be kept at reset value

Bit 20 PE4: PHY Error 4

Bit 19 PE3: PHY Error 3

Bit 18 PE2: PHY Error 2

Bit 17 PE1: PHY Error 1

Bit 16 PE0: PHY Error 0

Bit 15 AE15: Acknowledge Error 15

Bit 14 AE14: Acknowledge Error 14

Bit 13 AE13: Acknowledge Error 13

Bit 12 AE12: Acknowledge Error 12

Bit 11 AE11: Acknowledge Error 11

Bit 10 AE10: Acknowledge Error 10

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only

This bit indicates the status of phystopstateclklane D-PHY signal.

This bit indicates the status of phydirection D-PHY signal.

This bit indicates the LP1 contention error ErrContentionLP1 from lane 0.

This bit indicates the LP0 contention error ErrContentionLP0 from lane 0.

This bit indicates the ErrControl error from Lane 0.

This bit indicates the ErrSyncEsc Low-Power transmission synchronization error from

This bit indicates the ErrEsc escape entry error from lane 0.

This bit retrieves the DSI protocol violation from the Acknowledge error report.

This bit retrieves the reserved (specific to the device) from the Acknowledge error report.

This bit retrieves the invalid transmission length from the Acknowledge error report.

This bit retrieves the DSI VC ID Invalid from the Acknowledge error report.

This bit retrieves the not recognized DSI data type from the Acknowledge error report.

This bit retrieves the checksum error (long packet only) from the Acknowledge error

RM0432 Rev 6

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