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RM0432
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 PF[2:0]: pixel format
These bits configure the pixel format
000: ARGB8888
001: RGB888
010: RGB565
011: ARGB1555
100: ARGB4444
101: L8 (8-bit luminance)
110: AL44 (4-bit alpha, 4-bit luminance)
111: AL88 (8-bit alpha, 8-bit luminance)
29.8.19
LTDC layer x constant alpha configuration register
(LTDC_LxCACR)
This register defines the constant alpha value (divided by 255 by hardware), that is used in
the alpha blending. Refer to LTDC_LxBFCR register.
Address offset: 0x98 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 00FF
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 CONSTA[7:0]: constant alpha
These bits configure the constant alpha used for blending. The constant alpha is divided by
255 by hardware.
Example: if the programmed constant alpha is 0xFF, the constant alpha value is
255 / 255 = 1.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0432 Rev 6
LCD-TFT display controller (LTDC)
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
CONSTA[7:0]
rw
rw
rw
rw
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
rw
rw
rw
915/2301
0
rw
923
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