ST STM32L4+ Series Reference Manual page 350

General-purpose I/Os (GPIO)
Offset Register name
GPIOx_ODR
(where x = A..I)
0x14
Reset value
GPIOx_BSRR
(where x = A..I)
0x18
Reset value
GPIOx_LCKR
(where x = A..I)
0x1C
Reset value
GPIOx_AFRL
(where x = A..I)
0x20
Reset value
GPIOx_AFRH
(where x = A..I)
0x24
Reset value
GPIOx_BRR
(where x = A..I))
0x28
Reset value
Refer to
350/2301
Table 44. GPIO register map and reset values (continued)
0 0 0 0 0 0 0 0
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
0 0 0 0 0 0 0 0
AFSEL15[3:0 AFSEL14[3:0
] ]
0 0 0 0 0 0 0 0
Section 2.2 on page 91
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
AFSEL13[3:0 AFSEL12[3:0 AFSEL11[3:0
] ]
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0
for the register boundary addresses.
RM0432 Rev 6
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
]
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
RM0432