ST STM32L4+ Series Reference Manual page 461

RM0432
14.5 Graphic MMU registers
14.5.1 Graphic MMU configuration register (GFXMMU_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 192BM: 192 Block mode
Bit 5 Reserved, must be kept at reset value.
Bit 4 AMEIE: AHB master error interrupt enable
Bit 3 B3OIE: Buffer 3 overflow interrupt enable
Bit 2 B2OIE: Buffer 2 overflow interrupt enable
Bit 1 B1OIE: Buffer 1 overflow interrupt enable
Bit 0 B0OIE: Buffer 0 overflow interrupt enable
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
This bit defines the number of blocks per line
0: 256 blocks per line
1: 192 blocks per line
This bit enables the AHB master error interrupt.
0: Interrupt disable
1: Interrupt enabled
This bit enables the buffer 3 overflow interrupt.
0: Interrupt disable
1: Interrupt enabled
This bit enables the buffer 2 overflow interrupt.
0: Interrupt disable
1: Interrupt enabled
This bit enables the buffer 1 overflow interrupt.
0: Interrupt disable
1: Interrupt enabled
This bit enables the buffer 0 overflow interrupt.
0: Interrupt disable
1: Interrupt enabled
RM0432 Rev 6
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Res. 192BM Res. AMEIE
rw rw
Chrom-GRC™ (GFXMMU)
19 18 17
Res. Res. Res.
3 2 1
B3OIE B2OIE B1OIE
rw rw rw
461/2301
16
Res.
0
B0OIE
rw
467