ST STM32L4+ Series Reference Manual page 445

RM0432
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 RBS: Red Blue Swap
Bit 20 AI: Alpha Inverted
Bits 19:10 Reserved, must be kept at reset value.
Bit 9 SB: Swap Bytes
Bits 8:3 Reserved, must be kept at reset value.
Bits 2:0 CM[2: 0]: Color mode
13.5.15 DMA2D output color register (DMA2D_OCOLR)
Address offset: 0x0038
Reset value: 0x0000 0000
31 30 29 28
ALPHA[7:0]
rw rw rw rw
15 14 13 12
GREEN[7:0]
RED[4:0]
A RED[4:0]
ALPHA[3:0]
rw rw rw rw
This bit allows to swap the R & B to support BGR or ABGR color formats. Once the
transfer has started, this bit is read-only.
0: Regular mode (RGB or ARGB)
1: Swap mode (BGR or ABGR)
This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
0: Regular alpha
1: Inverted alpha
When set, the bytes in the output FIFO are swapped two by two.
When this bit is set, the number of pixel per line (PL) must be even, and the output
memory address (OMAR) must be even.
This register can only be written when the transfer is disabled. Once the transfer has
started, this register is read-only.
0: Bytes in regular order in the output FIFO
1: Bytes are swapped two by two in the output FIFO
These bits define the color format of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
000: ARGB8888
001: RGB888
010: RGB565
011: ARGB1555
100: ARGB4444
others: meaningless
27 26 25 24
rw rw rw rw
11 10 9 8
GREEN[5:0]
RED[3:0]
rw rw rw rw
RM0432 Rev 6
Chrom-ART Accelerator controller (DMA2D)
23 22 21
rw rw rw
7 6 5
GREEN[4:0]
GREEN[3:0]
rw rw rw
20 19 18 17
RED[7:0]
rw rw rw rw
4 3 2 1
BLUE[7:0]
BLUE[4:0]
BLUE[4:0]
BLUE[3:0]
rw rw rw rw
16
rw
0
rw
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