ST STM32L4+ Series Reference Manual page 500

Flexible static memory controller (FSMC)
18.6.1 NOR/PSRAM address mapping
HADDR[27:26] bits are used to select one of the four memory banks as shown in
1. HADDR are internal AHB address lines that are translated to external memory.
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.
Memory width
8-bit
16-bit
500/2301
Figure 47. FMC memory banks
Address
0x6000 0000
0x6FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF
0x9000 0000
0x9FFF FFFF
Table 83. NOR/PSRAM bank selection
(1)
HADDR[27:26]
00
01
10
11
Table 84. NOR/PSRAM External memory address
(1)
Data address issued to the memory
HADDR[25:0]
HADDR[25:1] >> 1
RM0432 Rev 6
Supported memory type
Bank
Bank 1
4 x 64 Mbyte
Not used
Bank 3
4 x 64 Mbyte
Not used
Selected bank
Bank 1 - NOR/PSRAM 1
Bank 1 - NOR/PSRAM 2
Bank 1 - NOR/PSRAM 3
Bank 1 - NOR/PSRAM 4
Maximum memory capacity (bits)
RM0432
NOR/PSRAM/SRAM
NAND Flash memory
MSv34475V2
Table
64 Mbytes x 8 = 512 Mbit
64 Mbytes/2 x 16 = 512 Mbit
83.