ST STM32L4+ Series Reference Manual page 530

Flexible static memory controller (FSMC)
Figure 65. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)
HCLK
CLK
A[25:16]
NEx
Hi-Z
NOE
NWE
NADV
NWAIT
(WAITCFG = 0)
A/D[15:0]
1 clock 1 clock
1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Table 111. FMC_BCRx bitfields (Synchronous multiplexed write mode)
Bit number
31:24
23:22
21
20
19
18:16
15
14
530/2301
Memory transaction = burst of 2 half words
addr[25:16]
(DATLAT + 2)
CLK cycles
Addr[15:0]
Bit name
Reserved 0x000
NBLSET[1:0] Don't care
WFDIS As needed
CCLKEN As needed
CBURSTRW 0x1
CPSIZE As needed (0x1 for CRAM 1.5)
ASYNCWAIT 0x0
EXTMOD 0x0
RM0432 Rev 6
inserted wait state
data
Value to set
RM0432
data
ai14731f