ST STM32L4+ Series Reference Manual page 417

RM0432
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Area filling with a fixed color
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Copy from an area to another
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Copy with pixel format conversion between source and destination images
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Copy from two sources with independent color format and blending
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Output buffer byte swapping to support refresh of displays through parallel interface
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Abort and suspend of DMA2D operations
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Watermark interrupt on a user programmable destination line
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Interrupt generation on bus error or access conflict
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Interrupt generation on process completion
13.3 DMA2D functional description
13.3.1 General description
The DMA2D controller performs direct memory transfer. As an AHB master, it can take the
control of the AHB bus matrix to initiate AHB transactions.
The DMA2D can operate in the following modes:
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Register-to-memory
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Memory-to-memory
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Memory-to-memory with Pixel Format Conversion
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Memory-to-memory with Pixel Format Conversion and Blending
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Memory-to memory with pixel format conversion, blending and fixed color foreground
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Memory-to memory with pixel format conversion, blending and fixed color background
The AHB slave port is used to program the DMA2D controller.
The block diagram of the DMA2D is shown in
Chrom-ART Accelerator controller (DMA2D)
Figure 35: DMA2D block
RM0432 Rev 6
diagram.
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