ST STM32L4+ Series Reference Manual page 362

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System configuration controller (SYSCFG)

SYSCFG SRAM2 write protection register (SYSCFG_SWPR)

Address offset: 0x20

System reset value: 0x0000 0000

P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP

P15WP P14WP P13WP P12WP P11WP P10WP P9WP

Bits 31:0 PxWP (x = 0 to 31): SRAM2 page x write protection

SYSCFG SRAM2 key register (SYSCFG_SKR)

Address offset: 0x24

System reset value: 0x0000 0000

Bit 2 PVDL: PVD lock enable bit

This bit is set by software and cleared only by a system reset. It can be used to

enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as

the PVDE and PLS[2:0] in the PWR_CR2 register.

0: PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and

PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0]

bits are read only.

Bit 1 SPL: SRAM2 parity lock bit

This bit is set by software and cleared only by a system reset. It can be used to

enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17

Break inputs.

0: SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs

1: SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs

Bit 0 CLL: Cortex

-M4 LOCKUP (Hardfault) output enable bit

This bit is set by software and cleared only by a system reset. It can be used to

enable and lock the connection of Cortex

TIM1/8/15/16/17 Break input

-M4 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs

-M4 LOCKUP output connected to TIM1/8/15/16/17 Break inputs

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 page x is disabled.

1: Write protection of SRAM2 page x is enabled.

RM0432 Rev 6

-M4 LOCKUP (Hardfault) output to

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