ST STM32L4+ Series Reference Manual page 524

Flexible static memory controller (FSMC)
1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then:
DATAST
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 61
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).
1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.
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DATAST ≥
max_wait_assertion_time
(
≥ ( × )
4 HCLK + max_wait_assertion_time
and show the number of HCLK clock cycles that are added to the
Figure 62
Figure 61. Asynchronous wait during a read access waveforms
A[25:0]
address phase
NEx
NWAIT don't care
NOE
D[15:0]
( 4 × HCLK ) max_wait_assertion_time
+
>
address_phase
≥ ×
DATAST 4 HCLK
Memory transaction
data setup phase
RM0432 Rev 6
+ hold_phase
– –
address_phase
don't care
data driven by memory
4HCLK
RM0432
)
hold_phase
MS30463V2