ST STM32L4+ Series Reference Manual page 566

Octo-SPI interface (OCTOSPI)
CS#
CK
RWDS
DQ[7:0]
The specific HyperBus features are configured through the registers in the 0x0200-0x02FC
offset range.
Command/address phase
During this initial phase, the OCTOSPI sends 48 bits over IO[7:0] to specify the operations
to be performed with the external device.
CA bit
47
46
45
44-16
15-3
2-0
The address space is configured through the memory type MTYP[2:0] field of the
OCTOSPI_DCR1 register.
The total size of the device is configured in the device size DEVSIZE[4:0] field of the
OCTOSPI_DCR1 register. In case of multi-chip product (MCP), the device size is the sum of
all the sizes of all the dies of the MCP.
Read and write operation with initial latency
The HyperBus read and write operations need to respect two timings:
•
t
RWR
OCTOSPI_HLCR)
• t
ACC
566/2301
Figure 75. Example of HyperBus read operation
t =Read Write Recovery
RWR
High = 2x Latency Count
Low = 1x Latency Count
47:40 39:32 31:24
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Table 120. Command/address phase description
Bit name
R/W# Identifies the transaction as a read or a write
Indicates if the transaction accesses the memory or the register
Address space
space
Burst type Indicates if the burst is linear or wrapped
Row and upper
Selects the row and the upper column addresses
column address
Reserved -
Lower column
Select the starting 16-bit word within the half page
address
: minimal read/write recovery time for the device (defined in TRWR[7:0] of
: access time for the device (defined in TAC[7:0] of OCTOSPI_HLCR)
t = Initial Access
ACC
Latency Count
23:16 15:8 7:0
RM0432 Rev 6
RWDS and Data
are edge aligned
Dn Dn
A B
Memory drives DQ[7:0]
and RWDS
Description
RM0432
Dn+1 Dn+1
A B
MSv43492V1