ST STM32L4+ Series Reference Manual page 798

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Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only

PSSI registers

An 8-bit write or a 16-bit write operation to any PSSI register besides PSSI_DR will result in

a bus error. 32-bit read and write operations are permitted.

PSSI control register (PSSI_CR)

Address offset: 0x00

Reset value: 0x4000 0000

Bits 29:21 Reserved, must be kept at reset value.

Bits 20:18 DERDYCFG: Data enable and ready configuration

Bits 17:15 Reserved, must be kept at reset value.

Bit 31 OUTEN: Data direction selection bit

0: Receive mode: data is input synchronously with PSSI_PDCK

1: Transmit mode: data is output synchronously with PSSI_PDCK

Bit 30 DMAEN: DMA enable bit

0: DMA transfers are disabled. The user application can directly access the

PSSI_DR register when DMA transfers are disabled.

1: DMA transfers are enabled (default configuration). A DMA channel in the

general-purpose DMA controller must be configured to perform transfers from/to

000: PSSI_DE and PSSI_RDY both disabled

001: Only PSSI_RDY enabled

010: Only PSSI_DE enabled

011: Both PSSI_RDY and PSSI_DE alternate functions enabled

100: Both PSSI_RDY and PSSI_DE features enabled - bidirectional on

PSSI_RDY pin (see

101: Only PSSI_RDY function enabled, but mapped to PSSI_DE pin

110: Only PSSI_DE function enabled, but mapped to PSSI_RDY pin

111: Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE

Bidirectional PSSI_DE/PSSI_RDY signal on page

When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or

111), it is still the RDYPOL bit which determines its polarity. Similarly, when the

PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still

the DEPOL bit which determines its polarity.

Bidirectional PSSI_DE/PSSI_RDY signal on page

RM0432 Rev 6

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