ST STM32L4+ Series Reference Manual page 573

RM0432
The access to the device begins in the same manner as in Indirect-read mode. The BUSY
bit in OCTOSPI_SR goes high at this point and stays high even between the periodic
accesses.
The content of MASK[31:0] in OCTOSPI_PSMAR is used to mask the data from the
external device in Automatic-polling mode:
•
If the MASK[n] = 0, then bit n of the result is masked and not considered.
• If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n] in
OCTOSPI_PSMAR, /°then there is a match for bit n.
If the polling match mode PMM bit in OCTOSPI_CR is 0, the AND-match mode is activated:
the status match flag (SMF) is set in OCTOSPI_SR only when there is a match on all of the
unmasked bits.
If PMM = 1 in OCTOSPI_CR, the OR-match mode is activated: SMF gets set if there is a
match on any of the unmasked bits.
An interrupt is called when SMF = 1 if SMIE = 1.
If the Automatic-polling mode stop APMS bit is set in OCTOSPI_CR, the operation stops
and BUSY goes to 0 as soon as a match is detected. Otherwise, BUSY stays at 1 and the
periodic accesses continue until there is an abort or until the OCTOSPI is disabled (EN = 0).
The OCTOSPI_DR register contains the latest received status bytes (FIFO deactivated).
The content of this register is not affected by the masking used in the matching logic. The
FTF status bit in OCTOSPI_SR is set as soon as a new reading of the status is complete.
FTF is cleared as soon as the data is read.
In Automatic-polling mode, variable latency is not supported. As a consequence, the
memory must be configured in Fixed latency.
19.4.10 OCTOSPI Memory-mapped mode
When configured in Memory-mapped mode, the external SPI device is seen as an internal
memory.
Note: More than 256 Mbytes can be addressed even if the external device capacity is larger.
If an access is made to an address outside of the range defined by DEVSIZE[4:0] but still
within the 256 Mbytes range, then an AHB error is given. The effect of this error depends on
the AHB master that attempted the access:
• If it is the Cortex CPU, a hard-fault interrupt is generated.
•
If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is
automatically disabled.
Byte, half-word, and word access types are all supported.
A support for execute in place (XIP) operation is implemented, where the OCTOSPI
continues to load the bytes to the addresses following the most recent access. If
subsequent accesses are continuous to the bytes that follow, then these operations ends up
quickly since their results were pre-fetched.
By default, the OCTOSPI never stops its prefetch operation, it either keeps the previous
read operation active with the nCS maintained low or it relaunches a new transfer, even if no
access to the external device occurs for a long time.
Since external devices tend to consume more when the nCS is held low, the application
may want to activate the timeout counter (TCEN = 1 in OCTOSPI_CR): the nCS is released
RM0432 Rev 6
Octo-SPI interface (OCTOSPI)
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