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RM0432
Reset value: 0x0000 0000
Access: 3 additional APB cycles are needed to write this register vs. a standard APB write.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 CSBF: Clear standby flag
Setting this bit clears the SBF flag in the PWR_SR1 register.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 CWUF5: Clear wakeup flag 5
Setting this bit clears the WUF5 flag in the PWR_SR1 register.
Bit 3 CWUF4: Clear wakeup flag 4
Setting this bit clears the WUF4 flag in the PWR_SR1 register.
Bit 2 CWUF3: Clear wakeup flag 3
Setting this bit clears the WUF3 flag in the PWR_SR1 register.
Bit 1 CWUF2: Clear wakeup flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register.
Bit 0 CWUF1: Clear wakeup flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register.
5.4.8
Power Port A pull-up control register (PWR_PUCRA)
Address offset: 0x20.
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register)
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
Res.
Res.
Res.
Res.
15
14
13
PU15
Res.
PU13
PU12
rw
rw
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
PU11
PU10
PU9
rw
rw
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
CSBF
Res.
Res.
w
24
23
22
Res.
Res.
Res.
8
7
6
PU8
PU7
PU6
rw
rw
rw
RM0432 Rev 6
Power control (PWR)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
CWUF
CWUF
CWUF
Res.
5
4
3
w
w
w
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PU5
PU4
PU3
PU2
rw
rw
rw
rw
17
16
Res.
Res.
1
0
CWUF
CWUF
2
1
w
w
17
16
Res.
Res.
1
0
PU1
PU0
rw
rw
225/2301
237
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