ST STM32L4+ Series Reference Manual page 804

Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only
25.5.8 PSSI register map
Table 170
Offset Register
PSSI_CR
0x00
Reset value 0 1
PSSI_SR
0x04
Reset value
PSSI_RIS
0x08
Reset value
PSSI_IER
0x0C
Reset value
PSSI_MIS
0x10
Reset value
PSSI_ICR
0x14
Reset value
0x18
to Reserved
0x24
PSSI_DR
0x28
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x2C
to Reserved
0x3EC
Refer to
804/2301
summarizes the PSSI registers.
Table 170. PSSI register map and reset values
BYTE3
Section 2.2 on page 91
0 0 0 0
Res.
BYTE2
Res.
for the register boundary addresses.
RM0432 Rev 6
EDM
0 0 0 0 0
BYTE1 BYTE0
0 0
0
0
0
0