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ST STM32L4+ Series Reference Manual page 732

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Digital-to-analog converter (DAC)
22.4.7
DMA requests
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the
value of the DAC_DHRx register is transferred into the DAC_DORx register when the
transfer is complete, and a DMA request is generated.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, only the corresponding DMAENx bit must be set. In this way, the
application can manage both DAC channels in dual mode by using one DMA request and a
unique DMA channel.
As DAC_DHRx to DAC_DORx data transfer occurred before the DMA request, the very first
data has to be written to the DAC_DHRx before the first trigger event occurs.
DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgment for the first external trigger is received (first request), then no new request
is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set,
reporting the error condition. The DAC channelx continues to convert old data.
The software must clear the DMAUDRx flag by writing 1, clear the DMAEN bit of the used
DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly.
The software must modify the DAC trigger conversion frequency or lighten the DMA
workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by
enabling both DMA data transfer and conversion trigger.
For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit
in the DAC_CR register is enabled.
22.4.8
DAC noise generation
In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVEx[1:0] to 01. The
preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after
each trigger event, following a specific calculation algorithm.
732/2301
RM0432 Rev 6
RM0432

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