ST STM32L4+ Series Reference Manual page 965

RM0432
30.12.4 DSI PLL control
The dedicated DSI PLL is controlled through the DSI Wrapper, as shown in
(analog blocks and signals in pink, digital signals in black, digital blocks in light blue).
CLKIN
3
IDF<2:0>
ENABLE
INFOUT
REFOUT
The PLL output frequency is configured through the DSI_WRPCR register fields. The VCO
frequency and the PLL output frequency are calculated as follows:
where:
• CLK
•
DSI_WRPCR.NDIV is in the range of 10 to 125;
• DSI_WRPCR.IDF is in the range of 1 to 7;
•
INFIN is in the range of 4 to 25 MHz;
• F
VCO
•
DSI_WRPCR.ODF can be 1, 2, 4 or 8;
• PHI is in the range of 31.25 to 500 MHz.
The PLL is enabled setting the PLLEN bit in the DSI_WRPCR register.
Once the PLL is locked, the PLLLIF bit is set in the DSI_WISR. If the PLLLIE bit is set in the
DSI_WIER, an interrupt is generated.
The PLL status (lock or unlock) can be monitored with the PLLLS flag in the DSI_WISR
register.
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
Figure 236. PLL block diagram
avddpll1v2 agndpll1v2
Input Frequency Divider
3 bit divider (IDF)
INFIN
Buffer PFD
Loop Frequency Divider
7 bit Divider
FBCLK
NDIV<6:0>
F
is in the range of 4 to 100 MHz;
IN
is in the range of 500 MHz to 1 GHz;
dvddpll1v2
INFIN
FBCLK
CPUMP
VCO
and LF
LS
DIV 2
(LDF)
7
= (CLK / IDF) * 2 * NDIV,
VCO IN
PHI = F / (2 *ODF)
VCO
RM0432 Rev 6
Figure 236
dgndpll1v2
Lock
Detect
2
ODF<1:0>
ODF
1,2,4,8
LOCKP
PHI
MSv35895V1
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