ST STM32L4+ Series Reference Manual page 165

RM0432
3.7.15 Flash WRP1 area B address register (FLASH_WRP1BR)
Address offset: 0x4C
Reset value: 0xFFXX FFXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:24 Reserved, must be kept cleared
Bits 23:16 WRP1B_END: WRP second area "B" end offset
3.7.16 Flash WRP2 area B address register (FLASH_WRP2BR)
Address offset: 0x50
Reset value: 0xFFXX FFXX
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
DBANK=1
WRP1B_END contains the last page of the WRP second area for bank1.
DBANK=0
WRP1B_END contains the last page of the WPR second area for all memory.
Bits 15:8 Reserved, must be kept cleared
Bits 7:0 WRP1B_STRT: WRP second area "B" start offset
DBANK=1
WRP1B_STRT contains the last page of the WRP second area for bank1.
DBANK=0
WRP1B_STRT contains the last page of the WPR second area for all memory.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
24 23 22
Res.
rw rw
8 7 6
Res.
rw rw
24 23 22
Res.
rw rw
8 7 6
Res.
rw rw
RM0432 Rev 6
Embedded Flash memory (FLASH)
21 20 19 18
WRP1B_END[7:0]
rw rw rw rw
5 4 3 2
WRP1B_STRT[7:0]
rw rw rw rw
21 20 19 18
WRP2B_END[7:0]
rw rw rw rw
5 4 3 2
WRP2B_STRT[7:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
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