Advertisement
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.15.32 DSI Host Timeout Counter Configuration Register 5 (DSI_TCCR5)
Address offset: 0x008C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Bits 31: 16 Reserved, must be kept at reset value
Bits 15: 0 BTA_TOCNT: Bus-Turn-Around Timeout Counter
30.15.33 DSI Host Clock Lane Configuration Register (DSI_CLCR)
Address offset: 0x0094
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31: 2 Reserved, must be kept at reset value
Bit 1 ACR: Automatic Clock lane Control
Bit 0 DPCC: D-PHY Clock Control
1004/2301
28
27
26
25
Res.
Res.
Res.
12
11
10
9
This field sets a period for which the DSI Host keeps the link still, after completing a Bus-
Turn-Around. This period is measured in cycles of lanebyteclk. The counting starts when
the D-PHY enters the Stop state and causes no interrupts.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit enables the automatic mechanism to stop providing clock in the clock lane when
time allows.
0: Automatic Clock Lane control disabled
1: Automatic Clock Lane control enabled
This bit controls the D-PHY Clock state:
0: Clock Lane is in Low-Power mode
1: Clock Lane is running in High-Speed mode
24
23
22
Res.
Res.
Res.
8
7
6
BTA_TOCNT[15:0]
rw
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0432
17
16
Res.
Res.
1
0
17
16
Res.
Res.
1
0
ACR
DPCC
rw
rw
Advertisement
Need help?
Do you have a question about the STM32L4+ Series and is the answer not in the manual?