ST STM32L4+ Series Reference Manual page 800

Hide thumbs Also See for STM32L4+ Series:

Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only

Bits 31:4 Reserved, must be kept at reset value.

PSSI raw interrupt status register (PSSI_RIS)

Address offset: 0x08

Reset value: 0x0000 0000

PSSI_RIS gives the raw interrupt status. This register is read-only. When read, it returns the

status of the corresponding interrupt before masking with the PSSI_IER register value.

Bit 3 RTT1B: FIFO is ready to transfer one byte

1: FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means

that at least one valid data byte is in the FIFO. In transmit mode, this means that

there is at least one byte free in the FIFO.

0: FIFO is not ready for a 1-byte transfer

Bit 2 RTT4B: FIFO is ready to transfer four bytes

1: FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means

that at least four valid data bytes are in the FIFO. In transmit mode, this means

that there are at least four bytes free in the FIFO.

0: FIFO is not ready for a four-byte transfer

Bits 1:0 Reserved, must be kept at reset value.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 OVR_RIS: Data buffer overrun/underrun raw interrupt status

0: No overrun/underrun occurred

1: An overrun/underrun occurred: overrun in receive mode, underrun in transmit

This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR.

Bit 0 Reserved, must be kept at reset value.

RM0432 Rev 6

Need help?

Do you have a question about the STM32L4+ Series and is the answer not in the manual?