ST STM32L4+ Series Reference Manual page 760

Digital-to-analog converter (DAC)
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 TREFRESH2[7:0]: DAC channel2 refresh time (only valid in Sample and hold mode)
Refresh time= (TREFRESH[7:0]) x LSI clock period
Note: This register can be modified only when EN2=0.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 TREFRESH1[7:0]: DAC channel1 refresh time (only valid in Sample and hold mode)
Refresh time= (TREFRESH[7:0]) x LSI clock period
Note: This register can be modified only when EN1=0.
Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.
760/2301
These bits are available only on dual-channel DACs. Refer to
implementation.
RM0432 Rev 6
RM0432
Section 22.3: DAC