ST STM32L4+ Series Reference Manual page 909

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LTDC interrupt status register (LTDC_ISR)

This register returns the interrupt status flag.

Address offset: 0x38

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 RRIF: register reload interrupt flag

0: no register reload interrupt generated

1: register reload interrupt generated when a vertical blanking reload occurs (and the first line

after the active area is reached)

Bit 2 TERRIF: transfer error interrupt flag

0: no transfer error interrupt generated

1: transfer error interrupt generated when a bus error occurs

Bit 1 FUIF: FIFO underrun interrupt flag

0: no FIFO underrun interrupt generated.

1: FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is

read from the FIFO

Bit 0 LIF: line interrupt flag

0: no line interrupt generated

1: line interrupt generated when a programmed line is reached

LTDC Interrupt Clear Register (LTDC_ICR)

Address offset: 0x3C

Reset value: 0x0000 0000

RM0432 Rev 6

LCD-TFT display controller (LTDC)

CRRIF CTERRIF CFUIF

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