ST STM32L4+ Series Reference Manual page 120

Embedded Flash memory (FLASH)
Flash area
Main
memory
512 Kbytes
Information
block
3.3.2 Error code correction (ECC)
Dual-bank mode (DBANK=1, 64-bits data width)
Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The
ECC mechanism supports:
• One error detection and correction
•
Two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in
ECC register
When two errors are detected, a flag ECCD (ECC detection) is set in FLASH_ECCR
register. In this case, a NMI is generated.
When an ECC error is detected, the address of the failing double word and its associated
bank are saved in ADDR_ECC[20:0] and BK_ECC in the FLASH_ECCR register.
ADDR_ECC[2:0] are always cleared.
When ECCC or ECCD is set, ADDR_ECC and BK_ECC are not updated if a new ECC error
occurs. FLASH_ECCR is updated only when ECC flags are cleared.
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared.
120/2301
Table 11. Flash module - 512 Kbytes single-bank organization
Flash memory address
0x0800 0000 - 0x0800 1FFF
0x0800 2000 - 0x0800 3FFF
0x0800 4000 - 0x0800 5FFF
Bank 1
512 Kbytes
0x0807 E000 - 0x0807 FFFF
Bank 1 0x1FFF 0000 - 0x1FFF 6FFF
Bank 2 0x1FFF 8000 - 0x1FFF EFFF
Bank 1 0x1FFF 7000 - 0x1FFF 73FF
Bank 1 0x1FF0 0000 - 0x1FF0 000F
Bank 2 0x1FF0 1000 - 0x1FF0 100F
(FLASH_ECCR). If ECCCIE is set, an interrupt is generated.
RM0432 Rev 6
(128 bits read width)
-
-
-
-
Size (bytes) Name
8 K Page 0
8 K Page 1
8 K Page 2
-
-
-
-
8 K Page 127
28 K
System memory
28 K
1 K OTP area
16
Option bytes
16
RM0432
-
-
-
-
Flash