ST STM32L4+ Series Reference Manual page 240

Reset and clock control (RCC)
1. Software reset, triggered by setting the BDRST bit in the
register
2. V
DD
A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and
the RCC Backup domain control register.
6.2 Clocks
Four different clock sources can be used to drive the system clock (SYSCLK):
•
HSI16 (high speed internal)16 MHz RC oscillator clock
•
MSI (multispeed internal) RC oscillator clock
•
HSE oscillator clock, from 4 to 48 MHz
•
PLL clock
The MSI is used as system clock source after startup from Reset, configured at 4 MHz.
The devices have the following additional clock sources:
•
32 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop and Standby modes.
•
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK).
•
RC 48 MHz internal clock sources (HSI48) to potentially drive the USB FS, the
SDMMC and the RNG.
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the AHB frequency, the APB1 and APB2
domains. The maximum frequency of the AHB, the APB1 and the APB2 domains is
120 MHz.
240/2301
(RCC_BDCR).
or V power on, if both supplies have previously been powered off.
BAT
RM0432 Rev 6
RM0432
Backup domain control