ST STM32L4+ Series Reference Manual page 302

Reset and clock control (RCC)
Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3SMEN: SPI3 clocks enable during Sleep and Stop modes
Bit 14 SPI2SMEN: SPI2 clocks enable during Sleep and Stop modes
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes
Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep and Stop modes
Bits :6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: TIM7 timer clocks enable during Sleep and Stop modes
Bit 4 TIM6SMEN: TIM6 timer clocks enable during Sleep and Stop modes
Bit 3 TIM5SMEN: TIM5 timer clocks enable during Sleep and Stop modes
Bit 2 TIM4SMEN: TIM4 timer clocks enable during Sleep and Stop modes
Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes
302/2301
Set and cleared by software.
0: USART2 clocks disabled by the clock gating
1: USART2 clocks enabled by the clock gating
Set and cleared by software.
0: SPI3 clocks disabled by the clock gating
1: SPI3 clocks enabled by the clock gating
Set and cleared by software.
0: SPI2 clocks disabled by the clock gating
1: SPI2 clocks enabled by the clock gating
Set and cleared by software. This bit is forced to '1' by hardware when the hardware WWDG
option is activated.
0: Window watchdog clocks disabled by the clock gating
1: Window watchdog clocks enabled by the clock gating
Set and cleared by software
0: RTC APB clock disabled by the clock gating
1: RTC APB clock enabled by the clock gating
Set and cleared by software.
0: TIM7 clocks disabled by the clock gating
1: TIM7 clocks enabled by the clock gating
Set and cleared by software.
0: TIM6 clocks disabled by the clock gating
1: TIM6 clocks enabled by the clock gating
Set and cleared by software.
0: TIM5 clocks disabled by the clock gating
1: TIM5 clocks enabled by the clock gating
Set and cleared by software.
0: TIM4 clocks disabled by the clock gating
1: TIM4 clocks enabled by the clock gating
Set and cleared by software.
0: TIM3 clocks disabled by the clock gating
1: TIM3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
RM0432 Rev 6
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
RM0432