ST STM32L4+ Series Reference Manual page 393

RM0432
11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)
Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: number of data to transfer (0 to 2
This field is updated by hardware when the channel is enabled:
If this field is zero, no transfer can be served whatever the channel status (enabled or not).
Note: this field is set and cleared by software.
11.6.5 DMA channel x peripheral address register (DMA_CPARx)
Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
27 26 25
Res. Res. Res.
11 10 9
rw rw rw
– It is decremented after each single DMA 'read followed by write' transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
27 26 25
rw rw rw
11 10 9
rw rw rw
Direct memory access controller (DMA)
24 23 22
Res. Res. Res. Res.
8 7 6
NDT[15:0]
rw rw rw
16
- 1)
24 23 22
PA[31:16]
rw rw rw
8 7 6
PA[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
17 16
rw rw
1 0
rw rw
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