ST STM32L4+ Series Reference Manual page 304

Reset and clock control (RCC)
6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR)
Address: 0x80
Reset value: 0x0D67 7801
Access: word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
USART TIM8S SPI1S
Res.
1SMEN MEN MEN
rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 DSISMEN: DSI clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DSI clocks disabled by the clock gating
1: DSI clocks enabled by the clock gating
Bit 26 LTDCSMEN: LCD-TFT timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LCD-TFT clocks disabled by the clock gating
1: LCD-TFT clocks enabled by the clock gating
Bit 25 Reserved, must be kept at reset value.
Bit 24 DFSDM1SMEN: DFSDM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DFSDM1 clocks disabled by the clock gating
1: DFSDM1 clocks enabled by the clock gating
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2SMEN: SAI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI2 clocks disabled by the clock gating
1: SAI2 clocks enabled by the clock gating
Bit 21 SAI1SMEN: SAI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI1 clocks disabled by the clock gating
1: SAI1 clocks enabled by the clock gating
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: TIM17 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM17 timer clocks disabled by the clock gating
1: TIM17 timer clocks enabled by the clock gating
304/2301
28 27 26 25
.DSISM LTDCS
Res.
EN MEN
rw rw
12 11 10 9
TIM1S
Res. Res.
MEN
rw rw
24 23 22
DFSD
SAI2S SAI1S
M1SM Res.
MEN MEN
EN
rw rw
8 7 6
Res. Res. Res.
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
(1)
RM0432 Rev 6
21 20 19 18
TIM17S
Res. Res.
MEN
rw rw
5 4 3 2
Res. Res. Res. Res.
during Sleep and Stop modes
during Sleep and Stop modes
RM0432
17 16
TIM16S TIM15S
MEN MEN
rw rw
1 0
SYSCF
Res. GSME
N
rw