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DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.15.57 DSI Host Video Line Current Configuration Register (DSI_VLCCR)
Address offset: 0x0150
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Bits 31: 15 Reserved, must be kept at reset value
Bits 14: 0 HLINE: Horizontal Line duration
30.15.58 DSI Host Video VSA Current Configuration Register
(DSI_VVSACCR)
Address offset: 0x0154
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31: 10 Reserved, must be kept at reset value
Bits 9: 0 VSA: Vertical Synchronism Active duration
1024/2301
28
27
26
25
Res.
Res.
Res.
12
11
10
9
This fields return the current total of the Horizontal Line period (HSA+HBP+HACT+HFP)
counted in lane byte clock cycles.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
This fields return the current Vertical Synchronism Active period measured in number of
horizontal lines.
24
23
22
Res.
Res.
Res.
8
7
6
HLINE[14:0]
ro
24
23
22
Res.
Res.
Res.
8
7
6
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
VSA[9:0]
ro
RM0432
17
16
Res.
Res.
1
0
17
16
Res.
Res.
1
0
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