ST STM32L4+ Series Reference Manual page 654

Analog-to-digital converters (ADC)
ADSTART (1)
EOC
EOS
OVR
ADSTP
(1)
TRGx
RDY
ADC state (2)
ADC_DR read access
ADC_DR
(OVRMOD=0)
ADC_DR
(OVRMOD=1)
by s/w
Note: There is no overrun detection on the injected channels since there is a dedicated data
register for each of the four injected channels.
Managing a sequence of conversions without using the DMA
If the conversions are slow enough, the conversion sequence can be handled by the
software. In this case the software must use the EOC flag and its associated interrupt to
handle each data. Each time a conversion is complete, EOC is set and the ADC_DR
register can be read. OVRMOD should be configured to 0 to manage overrun events as an
error.
Managing conversions without using the DMA and without overrun
It may be useful to let the ADC convert one or more channels without reading the data each
time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be
configured to 1 and OVR flag should be ignored by the software. An overrun event will not
prevent the ADC from continuing to convert and the ADC_DR register will always contain
the latest conversion.
Managing conversions using the DMA
Since converted channel values are stored into a unique data register, it is useful to use
DMA for conversion of more than one channel. This avoids the loss of the data already
stored in the ADC_DR register.
When the DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR register in single
ADC mode or MDMA different from 0b00 in dual ADC mode), a DMA request is generated
after each conversion of a channel. This allows the transfer of the converted data from the
ADC_DR register to the destination location selected by the software.
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Figure 121. Example of overrun (OVR)
CH1 CH2 CH3 CH4
D1
D2
D1 D2
by h/w
triggered
RM0432 Rev 6
CH5 CH6 CH7
Overun
D3
D4
D3 D4 D6
D5
RM0432
RDY
STOP
Indicative timings
MS31019V1