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ST STM32L4+ Series Reference Manual

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RM0432

Reference manual

®

STM32L4+ Series advanced Arm

-based

32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32L4+ Series microcontrollers memory and peripherals.

The STM32L4+ Series are families of microcontrollers with different memory sizes,

packages and peripherals.

For ordering information, mechanical and electrical device characteristics, refer to the

corresponding datasheets.

®

®

®

For information on the Arm

Cortex

-M4 core, refer to the Cortex

-M4 Technical Reference

Manual.

Related documents

®

• Cortex

-M4 Technical Reference Manual, available from: http://infocenter.arm.com

• STM32L4S5xx STM32L4S7xx STM32L4S9xx datasheet

• STM32L4R5xx STM32L4R7xx STM32L4R9xx datasheet

• STM32L4Q5xx datasheet

• STM32L4P5xx datasheet

®

• STM32F3, STM32F4, STM32L4 and STM32L4+ Series Cortex

-M4 (PM0214)

December 2019

RM0432 Rev 6

1/2301

www.st.com

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Summary of Contents for ST STM32L4+ Series

Page 1 This reference manual targets application developers. It provides complete information on how to use the STM32L4+ Series microcontrollers memory and peripherals. The STM32L4+ Series are families of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheets.
Page 2 Contents RM0432 Contents Documentation conventions ....... . . 84 General information ......... 84 List of abbreviations for registers .
Page 3 RM0432 Contents Introduction ..........113 FLASH main features .
Page 4 Contents RM0432 3.7.17 Flash configuration register (FLASH_CFGR) ....166 3.7.18 FLASH register map ........167 Firewall (FW) .
Page 5 RM0432 Contents 5.2.3 Peripheral Voltage Monitoring (PVM) ......194 Low-power modes ......... 195 5.3.1 Run mode .
Page 6 Contents RM0432 5.4.24 Power Port I pull-up control register (PWR_PUCRI) ....233 5.4.25 Power Port I pull-down control register (PWR_PDCRI) ... . 234 5.4.26 PWR control register (PWR_CR5) .
Page 7 RM0432 Contents 6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR) ... 270 6.4.7 Clock interrupt enable register (RCC_CIER) ....272 6.4.8 Clock interrupt flag register (RCC_CIFR) .
Page 8 Contents RM0432 CRS implementation ........321 CRS functional description .
Page 9 RM0432 Contents 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A to I) ..........342 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to I) .
Page 10 Contents RM0432 9.2.12 SYSCFG register map ........364 Peripherals interconnect matrix .
Page 11 RM0432 Contents 11.4.2 DMA pins and internal signals ....... 378 11.4.3 DMA transfers .
Page 12 Contents RM0432 12.6.4 DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) ........412 12.6.5 DMAMUX request generator interrupt status register (DMAMUX_RGSR) .
Page 13 RM0432 Contents 13.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) ..438 13.5.9 DMA2D foreground color register (DMA2D_FGCOLR) ... . 440 13.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) ..441 13.5.11 DMA2D background color register (DMA2D_BGCOLR) .
Page 14 Contents RM0432 14.5.11 Graphic MMU register map ....... . . 467 Nested vectored interrupt controller (NVIC) .
Page 15 RM0432 Contents 17.3 CRC functional description ........491 17.3.1 CRC block diagram .
Page 16 Contents RM0432 18.8.6 Computation of the error correction code (ECC) in NAND Flash memory ........546 18.8.7 NAND Flash controller registers .
Page 17 RM0432 Contents 19.6.6 OCTOSPI status register (OCTOSPI_SR) ..... . 588 19.6.7 OCTOSPI flag clear register (OCTOSPI_FCR) ....589 19.6.8 OCTOSPI data length register (OCTOSPI_DLR) .
Page 18 Contents RM0432 21.1 Introduction ..........612 21.2 ADC main features .
Page 19 RM0432 Contents 21.4.31 Dual ADC modes ......... 671 21.4.32 Temperature sensor .
Page 20 Contents RM0432 22.2 DAC main features ......... 725 22.3 DAC implementation .
Page 21 RM0432 Contents 22.7.12 DAC channel1 data output register (DAC_DOR1) ....753 22.7.13 DAC channel2 data output register (DAC_DOR2) ....754 22.7.14 DAC status register (DAC_SR) .
Page 22 Contents RM0432 24.5 DCMI registers ..........778 24.5.1 DCMI control register (DCMI_CR) .
Page 23 RM0432 Contents 26.2 COMP main features ........805 26.3 COMP functional description .
Page 24 Contents RM0432 Digital filter for sigma delta modulators (DFSDM) ....830 28.1 Introduction ..........830 28.2 DFSDM main features .
Page 25 RM0432 Contents 28.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR) ..870 28.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) ..872 28.8.5 DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) .
Page 26 Contents RM0432 29.8.2 LTDC back porch configuration register (LTDC_BPCR) ... 903 29.8.3 LTDC active width configuration register (LTDC_AWCR) ..904 29.8.4 LTDC total width configuration register (LTDC_TWCR) .
Page 27 RM0432 Contents 30.3 DSI Host main features ........925 30.4 DSI Host functional description .
Page 28 Contents RM0432 30.14.1 Programing procedure overview ......974 30.14.2 Configuring the D-PHY parameters ......974 30.14.3 Configuring the DSI host timing .
Page 29 RM0432 Contents 30.15.28 DSI Host Timeout Counter Configuration Register 1 (DSI_TCCR1) . 1001 30.15.29 DSI Host Timeout Counter Configuration Register 2 (DSI_TCCR2) . 1002 30.15.30 DSI Host Timeout Counter Configuration Register 3 (DSI_TCCR3) . 1002 30.15.31 DSI Host Timeout Counter Configuration Register 4 (DSI_TCCR4) . 1003 30.15.32 DSI Host Timeout Counter Configuration Register 5 (DSI_TCCR5) .
Page 30 Contents RM0432 30.15.59 DSI Host Video VBP Current Configuration Register (DSI_VVBPCCR) ........1025 30.15.60 DSI Host Video VFP Current Configuration Register (DSI_VVFPCCR) .
Page 31 RM0432 Contents 31.6.2 TSC interrupt enable register (TSC_IER) ..... 1056 31.6.3 TSC interrupt clear register (TSC_ICR) ..... . . 1057 31.6.4 TSC interrupt status register (TSC_ISR) .
Page 32 Contents RM0432 True random number generator (RNG) applied to STM32L4P5xx and STM32L4Q5xx only ..... . . 1078 33.1 Introduction ..........1078 33.2 RNG main features .
Page 33 RM0432 Contents 34.4.6 AES ciphertext stealing and data padding ..... 1105 34.4.7 AES task suspend and resume ......1105 34.4.8 AES basic chaining modes (ECB, CBC) .
Page 34 Contents RM0432 35.3 HASH implementation ........1145 35.4 HASH functional description .
Page 35 RM0432 Contents 36.4 PKA operating modes ........1173 36.4.1 Introduction .
Page 36 Contents RM0432 37.3.4 External trigger input ........1214 37.3.5 Clock selection .
Page 37 RM0432 Contents 37.4.9 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 1, 8) ........1272 37.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 1, 8) .
Page 38 Contents RM0432 38.3.4 Capture/Compare channels ....... . 1321 38.3.5 Input capture mode ........1323 38.3.6 PWM input mode .
Page 39 RM0432 Contents 38.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) ....1366 38.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) ..1366 38.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) .
Page 40 Contents RM0432 39.4.20 Slave mode – combined reset + trigger mode ....1412 39.4.21 DMA burst mode ........1412 39.4.22 Timer synchronization (TIM15) .
Page 41 RM0432 Contents 39.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 1449 39.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17) ..... . 1451 39.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) .
Page 42 Contents RM0432 41.1 Introduction ..........1477 41.2 LPTIM main features .
Page 43 RM0432 Contents 42.1 Introduction ..........1503 42.2 LPTIM main features .
Page 44 Contents RM0432 Infrared interface (IRTIM) ........1530 Independent watchdog (IWDG) .
Page 45 RM0432 Contents Real-time clock (RTC) applied to STM32L4Rxxx and STM32L4Sxxx only ..... . . 1546 46.1 Introduction ..........1546 46.2 RTC main features .
Page 46 Contents RM0432 46.6.13 RTC timestamp date register (RTC_TSDR) ....1580 46.6.14 RTC time-stamp sub second register (RTC_TSSSR) ... . 1581 46.6.15 RTC calibration register (RTC_CALR) .
Page 47 RM0432 Contents 47.6.3 RTC sub second register (RTC_SSR) ......1612 47.6.4 RTC initialization control and status register (RTC_ICSR) ..1612 47.6.5 RTC prescaler register (RTC_PRER) .
Page 48 Contents RM0432 48.6.4 TAMP interrupt enable register (TAMP_IER) ....1642 48.6.5 TAMP status register (TAMP_SR) ......1643 48.6.6 TAMP masked interrupt status register (TAMP_MISR) .
Page 49 RM0432 Contents 49.7.4 I2C own address 2 register (I2C_OAR2) ..... . 1708 49.7.5 I2C timing register (I2C_TIMINGR) ......1709 49.7.6 I2C timeout register (I2C_TIMEOUTR) .
Page 50 Contents RM0432 50.5.21 USART low-power management ......1764 50.6 USART interrupts ......... 1767 50.7 USART registers .
Page 51 RM0432 Contents 51.4.13 RS232 Hardware flow control and RS485 Driver Enable ..1827 51.4.14 LPUART low-power management ......1829 51.5 LPUART interrupts .
Page 52 Contents RM0432 52.4.14 CRC calculation ......... 1882 52.5 SPI interrupts .
Page 53 RM0432 Contents 53.6.2 SAI configuration register 1 (SAI_ACR1) ..... . 1932 53.6.3 SAI configuration register 1 (SAI_BCR1) ..... . 1935 53.6.4 SAI configuration register 2 (SAI_ACR2) .
Page 54 Contents RM0432 54.6.2 CMD12 send timing ........2001 54.6.3 Sleep (CMD5) .
Page 55 RM0432 Contents 55.3.2 Control, status and configuration registers ....2043 55.3.3 Tx mailboxes ......... . . 2043 55.3.4 Acceptance filters .
Page 56 Contents RM0432 56.4.1 OTG_FS block diagram ........2091 56.4.2 OTG_FS pin and internal signals .
Page 57 RM0432 Contents 56.15.6 OTG core interrupt register (OTG_GINTSTS) ....2126 56.15.7 OTG interrupt mask register (OTG_GINTMSK) ....2130 56.15.8 OTG receive status debug read register (OTG_GRXSTSR) .
Page 58 Contents RM0432 56.15.37 OTG device status register (OTG_DSTS) ..... 2163 56.15.38 OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) ........2164 56.15.39 OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) .
Page 59 RM0432 Contents 56.16.7 OTG programming model ....... . . 2240 Debug support (DBG) .
Page 60 57.17.7 Asynchronous mode ........2275 57.17.8 TRACECLKIN connection inside STM32L4+ Series ... . . 2275 57.17.9 TPIU registers .
Page 61 RM0432 List of tables List of tables Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses ............. 94 Table 2.
Page 62 SYSCFG register map and reset values........364 Table 47. STM32L4+ Series peripherals interconnect matrix ......366 Table 48.
Page 63 Table 118. FMC register map and reset values ......... 553 Table 119. OCTOSPI implementation on STM32L4+ Series ....... 556 Table 120.
Page 64 List of tables RM0432 Table 138. Oversampler operating modes summary ........670 Table 139.
Page 65 RM0432 List of tables Table 188. Filter maximum output resolution (peak data values from filter output) for some FOSR values ........... 850 Table 189.
Page 66 List of tables RM0432 Table 238. Processing time (in clock cycle) ......... . . 1156 Table 239.
Page 67 RM0432 List of tables Table 288. TIM16/TIM17 register map and reset values ....... . . 1462 Table 289.
Page 68 List of tables RM0432 Table 340. Examples of timing settings for fI2CCLK = 8 MHz ......1681 Table 341.
Page 69 RM0432 List of tables Table 391. Long response with CRC token format ........1974 Table 392.
Page 70 Figure 7. STM32L4+ Series firewall connection schematics ......170 Figure 8.
Page 71 RM0432 List of figures Figure 48. Mode 1 read access waveforms ..........507 Figure 49.
Page 72 List of figures RM0432 Figure 100. Injected conversion latency ..........637 Figure 101.
Page 73 RM0432 List of figures Figure 146. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode ... . 679 Figure 147. Alternate + regular simultaneous ......... . . 680 Figure 148.
Page 74 List of figures RM0432 Figure 195. Clock absence timing diagram for Manchester coding ......842 Figure 196.
Page 75 RM0432 List of figures Figure 247. Entropy source model ........... 1066 Figure 248.
Page 76 List of figures RM0432 Figure 299. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 ... . . 1210 Figure 300. Counter timing diagram, internal clock divided by N......1211 Figure 301.
Page 77 RM0432 List of figures Figure 351. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded)..1309 Figure 352. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded)..1310 Figure 353. Counter timing diagram, internal clock divided by 1 ......1311 Figure 354.
Page 78 List of figures RM0432 preloaded)............1384 Figure 402.
Page 79 RM0432 List of figures and Set-once mode activated (WAVE bit is set) ....... 1509 Figure 448.
Page 80 List of figures RM0432 Figure 496. Data sampling when oversampling by 8 ........1735 Figure 497.
Page 81 RM0432 List of figures Figure 541. Slave full-duplex communication ......... . 1876 Figure 542.
Page 82 List of figures RM0432 Figure 592. CMD12 stream timing ..........2003 Figure 593.
Page 83 RM0432 List of figures Figure 644. JTAG TAP connections ..........2252 Figure 645.
Page 84 Documentation conventions RM0432 Documentation conventions General information ®(a) ® The STM32L4+ Series devices have an Arm Cortex -M4 core. List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit.
Page 85 RM0432 Documentation conventions Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. • IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running.
Page 86 System and memory overview RM0432 System and memory overview System architecture The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Up to nine masters: ® – Cortex -M4 with FPU core I-bus ® – Cortex -M4 with FPU core D-bus ®...
Page 87 RM0432 System and memory overview Figure 1. System architecture for STM32L4Rxxx and STM32L4Sxxx ® Cortex DMA1 DMA2 DMA2D LCD-TFT SDMMC1 GFXMMU with FPU ICode FLASH 2 MB DCode SRAM1 SRAM2 SRAM3 GFXMMU AHB1 peripherals AHB2 peripherals FSMC OCTOSPI1 OCTOSPI2 BusMatrix-S MSv38490V1 RM0432 Rev 6 87/2301...
Page 88 System and memory overview RM0432 Figure 2. System architecture for STM32L4P5xx and STM32L4Q5xx ® Cortex DMA1 DMA2 DMA2D LCD-TFT SDMMC1 SDMMC2 with FPU ICode FLASH 2 MB DCode SRAM1 SRAM2 SRAM3 AHB1 peripherals AHB2 peripherals FSMC OCTOSPI1 OCTOSPI2 BusMatrix-S MSv61196V1 2.1.1 I-bus ®...
Page 89 RM0432 System and memory overview peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the FMC. The SRAM2 is also accessible on this bus to allow continuous mapping with SRAM1 and SRAM3. 2.1.4 DMA-bus This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this bus are the SRAM1,SRAM2 and SRAM3, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the FMC.
Page 90 System and memory overview RM0432 For STM32L4Rxxx and STM32L4Sxxx devices, the BusMatrix is composed of • up to nine masters: – CPU AHB system bus, D-Code bus, I-Code bus, DMA1, DMA2, DMA2D, SDMMC1, LCD-TFT and GFXMMU • up to eleven slaves: –...
Page 91 RM0432 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 92 RM0432 2.2.2 Memory map and register boundary addresses Figure 3. Memory map for STM32L4Rxxx and STM32L4Sxxx 0xFFFF FFFF 0xBFFF FFFF Reserved Cortex™-M4 0xA000 1800 with FPU OCTOSPI registers Internal 0xA000 1000 Peripherals FMC registers 0xA000 0000 0xE000 0000 0x5FFF FFFF Reserved Reserved 0x5006 0C00...
Page 93 RM0432 Figure 4. Memory map for STM32L4P5xx and STM32L4Q5xx 0xFFFF FFFF 0xBFFF FFFF Reserved Cortex™-M4 0xA000 1800 with FPU OCTOSPI registers Internal 0xA000 1000 Peripherals FMC registers 0xA000 0000 0xE000 0000 0x5FFF FFFF Reserved Reserved 0x5006 2C00 AHB2 0x4800 0000 0xC000 0000 Reserved 0x4002 BC00...
Page 94 RM0432 All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved” (highlighted in gray). For the detailed mapping of available memory and register areas, refer to the following table. The following table gives the boundary addresses of the peripherals available in the devices.
Page 95 RM0432 Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x5006 2000 - 0x5FFF FFFF ~260 MB Reserved 0x5006 2400 - 0x5006 27FF Section 54.9.20: SDMMC register 1 KB SDMMC1 0x5006 2000 - 0x5006 23FF 1 KB...
Page 96 RM0432 Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4002 F000 - 0x47FF FFFF ~127 MB Reserved 0x4002 C000 - 0x4002 EFFF GFXMMU Section 14.5.11: Graphic MMU register map 0x4002 BC00 - 0x4002 BBFF 1 KB...
Page 97 RM0432 Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4001 7400 - 0x4001 FFFF 33 KB Reserved 0x4001 6C00 - 0x4001 73FF 1 KB DSIHOST Section 30.17: DSI Host register map 0x4001 6800 - 0x4001 6BFF 1 KB LCD-TFT...
Page 98 RM0432 Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 Section 41.7.11: LPTIM register map 0x4000 8C00 - 0x4000 93FF 3 KB Reserved...
Page 99 RM0432 Table 1. STM32L4Rxxx and STM32L4Sxxx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 4800 - 0x4000 4BFF 1 KB USART3 Section 50.7.15: USART register map 0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 50.7.15: USART register map...
Page 100 RM0432 Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses Size Boundary address Peripheral Peripheral register map (bytes) 0xA000 1800 - 0xDFFF FFFF 1 KB Reserved OCTOSPI2 Section 19.6.24: OCTOSPI register 0xA000 1400 - 0xA000 17FF 1 KB registers OCTOSPI1 Section 19.6.24: OCTOSPI register...
Page 101 RM0432 Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x5006 2C00 - 0x5FFF FFFF ~260 MB Reserved 0x5006 2400 - 0x5006 27FF Section 54.9.20: SDMMC register 1 KB SDMMC1 0x5006 2800 - 0x5006 2BFF Section 54.9.20: SDMMC register...
Page 102 RM0432 Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4002 BC00 - 0x47FF FFFF ~127 MB Reserved 0x4002 B000 - 0x4002 BBFF Section 13.5.23: DMA2D register 3 KB DMA2D 0x4002 4400 - 0x4002 AFFF 26 KB...
Page 103 RM0432 Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4001 7400 - 0x4001 FFFF 33 KB Reserved 0x4001 6C00 - 0x4001 73FF 1 KB Reserved 0x4001 6800 - 0x4001 6BFF 1 KB LCD-TFT Section 29.8.26: LTDC register map...
Page 104 RM0432 Table 2. STM32L4P5xx and STM32L4Q5xx memory map and peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 9800 - 0x4000 FFFF 26 KB Reserved 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2 Section 41.7.11: LPTIM register map 0x4000 8C00 - 0x4000 93FF 3 KB Reserved...
Page 105 In the STM32L4+ Series devices both the peripheral registers and the SRAM1 are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The ®...
Page 106 RM0432 A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: – bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit –...
Page 107 RM0432 offering a continuous address space with the SRAM1 and SRAM3. 2.4.1 SRAM2 parity check The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the user option byte (refer to Section 3.4.1: Option bytes description). The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms.
Page 108 RM0432 Table 3. SRAM2 organization (continued) Page number Start address End address Page 18 0x1000 4800 0x1000 4BFF Page 19 0x1000 4C00 0x1000 4FFF Page 20 0x1000 5000 0x1000 53FF Page 21 0x1000 5400 0x1000 57FF Page 22 0x1000 5800 0x1000 5BFF Page 23 0x1000 5C00...
Page 109 The information block. It is composed of three parts: – Option bytes for hardware and memory protection user configuration. – System memory that contains the ST proprietary code. – OTP (one-time programmable) area The Flash interface implements instruction access and data access based on the AHB protocol.
Page 110 RM0432 (program/erase) controlled through the Flash registers Refer to Section 3: Embedded Flash memory (FLASH) for more details. Boot configuration 2.6.1 Boot configuration Three different boot modes can be selected through the BOOT0 pin or the nBOOT0 bit into the FLASH_OPTR register (if the nSWBOOT0 bit is cleared into the FLASH_OPTR register), and nBOOT1 bit in FLASH_OPTR register, as shown in the following table.
Page 111 RM0432 (0x0800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000. • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF 0000). •...
Page 112 5. 192 Kbytes for STM32L4Rxxx and STM32L4Sxxx devices and 128 Kbytes for STM32L4P5xx and STM32L4Q5xx devices. Embedded boot loader The embedded boot loader is located in the system memory, programmed by ST during production. Refer to AN2606 STM32 microcontroller system memory boot mode.
Page 113 RM0432 Embedded Flash memory (FLASH) Embedded Flash memory (FLASH) Introduction The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 114 Embedded Flash memory (FLASH) RM0432 FLASH functional description 3.3.1 Flash memory organization The Flash memory has the following main features: • Capacity up to 2 Mbytes, in Single-bank mode (read width of 128 bits) or in Dual-bank mode (read width of 64-bits) •...
Page 115 STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606 available from www.st.com. – 1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The OTP area is available in Bank 1 only.
Page 116 Embedded Flash memory (FLASH) RM0432 Table 6. Flash module - 2 Mbytes dual-bank organization (64 bits read width) Flash area Flash memory address Size (bytes) Name 0x0800 0000 - 0x0800 0FFF Page 0 0x0800 1000 - 0x0800 1FFF Page 1 0x0800 2000 - 0x0800 2FFF Page 2 0x0800 3000 - 0x0800 3FFF...
Page 117 RM0432 Embedded Flash memory (FLASH) Table 7. Flash module - 2 Mbytes single-bank organization (128 bits read width) Flash area Flash memory address Size (bytes) Name 0x0800 0000 - 0x0800 1FFF Page 0 0x0800 2000 - 0x0800 3FFF Page 1 0x0800 4000 - 0x0800 5FFF Page 2 Main memory...
Page 118 Embedded Flash memory (FLASH) RM0432 Table 8. Flash module - 1 Mbyte dual-bank organization (64 bits read width) Flash area Flash memory address Size (bytes) Name 0x0800 0000 - 0x0800 0FFF Page 0 0x0800 1000 - 0x0800 1FFF Page 1 0x0800 2000 - 0x0800 2FFF Page 2 0x0800 3000 - 0x0800 3FFF...
Page 119 RM0432 Embedded Flash memory (FLASH) Table 9. Flash module - 1 Mbyte single-bank organization (128 bits read width) (continued) Flash area Flash memory address Size (bytes) Name Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K System memory Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K Information...
Page 120 Embedded Flash memory (FLASH) RM0432 Table 11. Flash module - 512 Kbytes single-bank organization (128 bits read width) Flash area Flash memory address Size (bytes) Name 0x0800 0000 - 0x0800 1FFF Page 0 0x0800 2000 - 0x0800 3FFF Page 1 0x0800 4000 - 0x0800 5FFF Page 2 Main...
Page 121 RM0432 Embedded Flash memory (FLASH) Single-bank mode (DBANK=0, 128-bits data width) Data in Flash memory are 144-bits words: 8 bits are added per each double word. The ECC mechanism supports: • One error detection and correction • Two errors detection per 64 double words The user must first check the SYSF_ECC bit, and if it is set, the user must refer to the DBANK=1 programming model (because system Flash is always on 2 banks).
Page 122 Embedded Flash memory (FLASH) RM0432 Table 12. Number of wait states according to CPU clock (HCLK) frequency HCLK (MHz) Wait states (WS) (Latency) Range 1 Range 2 CORE CORE 0 WS (1 CPU cycles) ≤20 ≤8 1 WS (2 CPU cycles) ≤40 ≤16 2 WS (3 CPU cycles)
Page 123 RM0432 Embedded Flash memory (FLASH) To release the processor full performance, the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 64- bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 120 MHz.
Page 124 Embedded Flash memory (FLASH) RM0432 Figure 5. Sequential 16-bit instructions execution (64-bit read data width) WAIT WITHOUT PREFETCH WAIT ins 1 ins 2 ins 3 ins 4 ins 5 ins 6 ins 7 ins 8 fetch fetch fetch fetch fetch fetch fetch fetch...
Page 125 Data in option bytes block are not cacheable. 3.3.5 Flash program and erase operations The STM32L4+ Series embedded Flash memory can be programmed using in-circuit programming or in-application programming. The in-circuit programming (ICP) method is used to update the entire contents of the Flash memory, using the JTAG, SWD protocol or the bootloader to load the user application into the microcontroller.
Page 126 Embedded Flash memory (FLASH) RM0432 a write/erase operation is performed to the other bank (refer to Section 3.3.8: Read-while- write (RWW) available only in Dual-bank mode (DBANK=1)). The Flash erase and programming is only possible in the voltage scaling range 1. The VOS[1:0] bits in the PWR_CR1 must be programmed to 01b.
Page 127 RM0432 Embedded Flash memory (FLASH) Bank 1, Bank 2 Mass erase (available only in Dual-bank mode when DBANK=1) To perform a bank Mass Erase, follow the procedure below: Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register.
Page 128 Embedded Flash memory (FLASH) RM0432 Check that no Flash main memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR). Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. Set the PG bit in the Flash control register (FLASH_CR).
Page 129 RM0432 Embedded Flash memory (FLASH) bootloader. In Dual-bank mode (DBANK=1), perform a mass erase of the bank to program. If not, PGSERR is set. Check that no Flash main memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR).
Page 130 Embedded Flash memory (FLASH) RM0432 Programming errors Several kind of errors can be detected. In case of error, the Flash operation (programming or erasing) is aborted. • PROGERR: Programming error In standard programming: PROGERR is set if the word to write is not previously erased (except if the value to program is full zero).
Page 131 RM0432 Embedded Flash memory (FLASH) previous data programmation is finished and the next data to program is not written yet. • FASTERR: Fast programming error In fast programming: FASTERR is set if one of the following conditions occurs: – When FSTPG bit is set for more than 7ms which generates a time-out detection. –...
Page 132 Embedded Flash memory (FLASH) RM0432 Read from bank 1 while mass erasing bank 2 (or vice versa) While executing a program code from bank 1, it is possible to perform a mass erase operation on bank 2 (and vice versa). Follow the procedure below: Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR)
Page 133 RM0432 Embedded Flash memory (FLASH) FLASH option bytes 3.4.1 Option bytes description The option bytes are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode (refer to Section 3.4.2: Option bytes programming).
Page 134 WRP2A WRP2B 1FF01020 Unused Unused Unused Unused _END _STRT _END _STRT User and read protection option bytes Flash memory address: 0x1FF0 0000 ST production value: 0xFFEF F8AA SRAM2 SRAM2 WWDG IWGD_ IWDG_ IWDG_ Res. Res. Res. Res. DBANK DB1M BFB2...
Page 135 RM0432 Embedded Flash memory (FLASH) Bit 22 DBANK: 0: Single-bank mode with 128 bits data read width 1: Dual-bank mode with 64 bits data This bit can be written only when PCROP1/2 is disabled. Bit 21 DB1M: For STM32L4Rxxx and STM32L4Sxxx devices: Dual-bank on 1-Mbyte Flash memory devices 0: 1 Mbyte single Flash contiguous address in Bank1 1: 1 Mbyte dual-bank Flash with contiguous addresses...
Page 136 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active PCROP1 Start address option bytes Flash memory address: 0x1FF0 0008 ST production value: 0xFFFF FFFF PCROP Res. Res. Res.
Page 137 PCROP1_END contains the last double-word of the bank 1 PCROP area. DBANK=0 PCROP1_END contains the last 2x double-word PCROP area for all memory. WRP Area A address option bytes Flash memory address: 0x1FF0 0018 ST production value: 0x0000 00FF Res. Res. Res. Res.
Page 138 WRP1B_STRT contains the last page of the WRP second area for bank1. DBANK=0 WRP1B_STRT contains the last page of the WPR second area for all memory. PCROP2 Start address option bytes Flash memory address: 0x1FF0 1008 ST production value: 0xFFFF FFFF PCROP Res. Res. Res.
Page 139 PCROP2_END contains the last double-word of the PCROP area for bank2. DBANK=0 PCROP2_END contains the last 2xdouble-word of the PCROP area for all the memory. WRP2 Area A address option bytes Flash memory address: 0x1FF0 1018 ST production value: 0x0000 00FF Res. Res. Res. Res. Res.
Page 140 Embedded Flash memory (FLASH) RM0432 Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_END[23:16] Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_STRT[7:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 WRP2B_END: WRP second area “B” end offset DBANK=1 WRP2B_END contains the last page of the WRP second area for bank2.
Page 141 RM0432 Embedded Flash memory (FLASH) Flash PCROP2 Start address register (FLASH_PCROP2SR), Flash PCROP2 End address register (FLASH_PCROP2ER), Flash WRP2 area A address register (FLASH_WRP2AR), Flash WRP2 area B address register (FLASH_WRP2BR). Set the Options Start bit OPTSTRT in the Flash control register (FLASH_CR).
Page 142 Embedded Flash memory (FLASH) RM0432 corrupted data from the Flash when the memory organization is changed, any access (either CPU or DMAs) to Flash memory should be avoided before reprogramming. • Disable Instruction/data caches and/or prefetch if they are enabled (reset PRFTEN and ICEN/DCEN bits in the FLASH_ACR register).
Page 143 RM0432 Embedded Flash memory (FLASH) FLASH memory protection The Flash main memory can be protected against external accesses with the Read protection (RDP). The pages of the Flash memory can also be protected against unwanted write due to loss of program counter contexts. The write-protection (WRP) granularity is one page (2 KByte).
Page 144 Embedded Flash memory (FLASH) RM0432 Level 1: Read protection This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct.
Page 145 RM0432 Embedded Flash memory (FLASH) Note: Full Mass Erase or Partial Mass Erase is performed only when Level 1 is active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2) there is no mass erase. To validate the protection level change, the option bytes must be reloaded through the OBL_LAUNCH bit in Flash control register.
Page 146 Embedded Flash memory (FLASH) RM0432 Table 16. Access status versus protection level and execution modes (continued) Debug/ BootFromRam/ User execution (BootFromFlash) Protection BootFromLoader Area level Read Write Erase Read Write Erase Backup registers SRAM2 1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled. 2.
Page 147 RM0432 Embedded Flash memory (FLASH) For example, to protect by PCROP from the address 0x0806 2F80 (included) to the address 0x0807 0004 (included): • if boot in Flash is done in Bank 1, FLASH_PCROP1SR and FLASH_PCROP1ER registers must be programmed with: –...
Page 148 Embedded Flash memory (FLASH) RM0432 1. When DBANK=1, the minimum PCROP area size is 2xdouble words: PCROPx_offset_strt and PCROPx_offset_end. When DBANK=0, the minimum PCROP area size is 2x(2xdouble words): PCROPx_offset_strt and PCROPx_offset_end. When DBANK=1, it is the user’s responsibility to make sure no overlapping occurs on the PCROP zones. 3.5.3 Write protection (WRP) The user area in Flash memory can be protected against unwanted write operations.
Page 149 RM0432 Embedded Flash memory (FLASH) When WRP is active, it cannot be erased or programmed. Consequently, a software mass erase cannot be performed if one area is write-protected. If an erase/program operation to a write-protected part of the Flash memory is attempted, the write protection error flag (WRPERR) is set in the FLASH_SR register.
Page 150 Embedded Flash memory (FLASH) RM0432 FLASH registers 3.7.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0600 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 151 RM0432 Embedded Flash memory (FLASH) Bit 9 ICEN: Instruction cache enable 0: Instruction cache is disabled 1: Instruction cache is enabled Bit 8 PRFTEN: Prefetch enable 0: Prefetch disabled 1: Prefetch enabled Bits 7:4 Reserved, must be kept at reset value. Bits 3:0 LATENCY[:0]: Latency These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.
Page 152 Embedded Flash memory (FLASH) RM0432 3.7.3 Flash key register (FLASH_KEYR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word access KEYR[31:16] KEYR[15:0] Bits 31:0 KEYR: Flash key The following values must be written consecutively to unlock the FLACH_CR register allowing Flash programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB...
Page 153 RM0432 Embedded Flash memory (FLASH) 3.7.5 Flash status register (FLASH_SR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access PEMPT Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 154 Embedded Flash memory (FLASH) RM0432 Bit 8 MISERR: Fast programming data miss error In fast programming mode, 32 double words must be sent to Flash successively, and the new data must be sent to the Flash logic control before the current data is fully programmed.
Page 155 RM0432 Embedded Flash memory (FLASH) 3.7.6 Flash control register (FLASH_CR) Address offset: 0x14 Reset value: 0xC000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access OBL_ LOCK Res. Res. Res. Res. Res.
Page 156 Embedded Flash memory (FLASH) RM0432 Bits 23:19 Reserved, must be kept at reset value Bit 18 FSTPG: Fast programming 0: Fast programming disabled 1: Fast programming enabled Bit 17 OPTSTRT: Options modification start This bit triggers an options operation when set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_SR.
Page 157 RM0432 Embedded Flash memory (FLASH) 3.7.7 Flash ECC register (FLASH_ECCR) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state when no Flash memory operation is on going, word, half-word and byte access ECCC SYSF_ ECCD ECCD ECCC ECCD2 Res.
Page 158 Embedded Flash memory (FLASH) RM0432 Bit 24 ECCIE: ECC correction interrupt enable 0: ECCC interrupt disabled 1: ECCC interrupt enabled. DBANK=0 This bit enables the interrupt generation when the ECCC or ECCC2 bits in the FLASH_ECCR register are set. DBANK=1 This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set.
Page 159 RM0432 Embedded Flash memory (FLASH) 3.7.8 Flash option register (FLASH_OPTR) Address offset: 0x20 Reset value: 0xFFEF F8AA. Register bits are loaded with values from Flash memory at OBL. Access: no wait state when no Flash memory operation is on going; word, half-word and byte access IWDG_ SRAM2...
Page 160 Embedded Flash memory (FLASH) RM0432 Bit 21 DB1M: For STM32L4Rxxx and STM32L4Sxxx devices: Dual-bank on 1 Mbyte Flash memory devices 0: 1 Mbyte single Flash contiguous address in Bank 1 1: 1 Mbyte dual-bank Flash with contiguous addresses When DB1M is set, a hard fault is generated when the requested address goes over 1 Mbyte.
Page 161 RM0432 Embedded Flash memory (FLASH) Bit 11 Reserved, must be kept cleared Bits10:8 BOR_LEV: BOR reset Level These bits contain the VDD supply level threshold that activates/releases the reset. 000: BOR Level 0. Reset level threshold is around 1.7 V 001: BOR Level 1.
Page 162 Embedded Flash memory (FLASH) RM0432 3.7.10 Flash PCROP1 End address register (FLASH_PCROP1ER) Address offset: 0x28 Reset value: 0xXFFX XXXX. Register bits are loaded with values from Flash memory at OBL. Access: no wait state when no Flash memory operation is on going; word, half-word access. PCROP_RDP bit can be accessed with byte access.
Page 163 RM0432 Embedded Flash memory (FLASH) Bits 31:24 Reserved, must be kept cleared Bits 23:16 WRP1A_END: WRP first area “A” end offset DBANK=1 WRP1A_END contains the last page of WRP first area in bank1. DBANK=0 WRP1A_END contains the last page of WRP first area for all memory. Bits 15:8 Reserved, must be kept cleared Bits 7:0 WRP1A_STRT: WRP first area “A”...
Page 164 Embedded Flash memory (FLASH) RM0432 3.7.13 Flash PCROP2 Start address register (FLASH_PCROP2SR) Address offset: 0x44 Reset value: 0xFFFF FFFF Access: no wait state when no Flash memory operation is on going; word access. PCRO Res. Res. Res. Res. Res. Res. Res.
Page 165 RM0432 Embedded Flash memory (FLASH) 3.7.15 Flash WRP1 area B address register (FLASH_WRP1BR) Address offset: 0x4C Reset value: 0xFFXX FFXX. Register bits are loaded with values from Flash memory at OBL. Access: no wait state when no Flash memory operation is on going; word, half-word and byte access Res.
Page 166 Embedded Flash memory (FLASH) RM0432 Bits 31:24 Reserved, must be kept cleared Bits 23:16 WRP2B_END: WRP second area “B” end offset DBANK=1 WRP2B_END contains the last page of the WRP second area for bank2. DBANK=0 WRP2B_END contains the last page of the WRP fourth area for all memory. Bits 15:8 Reserved, must be kept cleared Bits 23:16 WRP2B_STRT: WRP second area “B”...
Page 167 RM0432 Embedded Flash memory (FLASH) 3.7.18 FLASH register map Table 20. Flash interface - register map and reset values Offset Register LATENCY FLASH_ACR [3:0] 0x00 Reset value FLASH_ PDKEYR[31:0] PDKEYR 0x04 Reset value FLASH_KEYR KEYR[31:0] 0x08 Reset value FLASH_OPT OPTKEYR[31:0] KEYR 0x0C Reset value...
Page 168 Embedded Flash memory (FLASH) RM0432 Table 20. Flash interface - register map and reset values (continued) Offset Register FLASH_ WRP2A_END[7:0] WRP2A_STRT[7:0] WRP2AR 0x30 Reset value X X X X X X X X X X X X X X X X FLASH_ PCROP2_STRT[16:0] PCROP2SR...
Page 169 RM0432 Firewall (FW) Firewall (FW) Introduction The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory, and/or to protect the Volatile data into the SRAM1 from the rest of the code executed outside the protected area. Firewall main features •...
Page 170 Firewall AMBA bus snoop The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and non-volatile) are connected. A global architecture view is illustrated in Figure Figure 7. STM32L4+ Series firewall connection schematics AHB Slave AHB Master 1 FLASH...
Page 171 RM0432 Firewall (FW) end code needs to embed an IAP located in a write protected segment in order to allow future code updates when the production parts will be Level 2 ROP. Write protection In order to offer a maximum security level, the following points need to be respected: •...
Page 172 Firewall (FW) RM0432 Volatile data segment Volatile data used by the protected code located into the code segment must be defined into the SRAM1 memory. The access to this segment is defined into the Section 4.3.4: Segment accesses and properties. Depending on the Volatile data segment configuration, the Firewall must be opened or not before accessing this segment area.
Page 173 RM0432 Firewall (FW) The Volatile data segment is a bit different from the two others. The segment can be: • Shared (VDS bit in the register) It means that the area and the data located into this segment can be shared between the protected code and the user code executed in a non-protected area.
Page 174 Firewall (FW) RM0432 Below is the initialization procedure to follow: Configure the RCC to enable the clock to the Firewall module Configure the RCC to enable the clock of the system configuration registers Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL, VDSSA, VDSL registers) Set the configuration register of the Firewall (FW_CR register) Enable the Firewall clearing the FWDIS bit in the system configuration register.
Page 175 RM0432 Firewall (FW) Opening the Firewall As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the protected segments are forbidden (refer to Section 4.3.4: Segment accesses and properties). In order to open the Firewall to interact with the protected segments, it is mandatory to apply the “call gate”...
Page 176 Firewall (FW) RM0432 Firewall registers 4.4.1 Code segment start address (FW_CSSA) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16] ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:24 Reserved, must be kept at reset value. Bits 23:8 ADD[23:8]: code segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity.
Page 177 RM0432 Firewall (FW) 4.4.3 Non-volatile data segment start address (FW_NVDSSA) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16] ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:24 Reserved, must be kept at the reset value. Bits 23:8 ADD[23:8]: Non-volatile data segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity.
Page 178 Firewall (FW) RM0432 4.4.5 Volatile data segment start address (FW_VDSSA) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. [17:16] ADD[15:6] Res. Res. Res. Res. Res. Res. Bits 31:18 Reserved, must be kept at the reset value. Bit 17 ADD[17]: Volatile data segment start address Bits 16:6 ADD[16:6]: Volatile data segment start address The LSB bits of the start address (bit 5:0) are reserved and forced to 0 in order to allow a...
Page 179 RM0432 Firewall (FW) Bits 31:18 Reserved, must be kept at the reset value. Bit 17 LENG[17]: volatile data segment length Bits 16:6 LENG[16:6]: volatile data segment length LENG[16:6] selects the size of the volatile data segment expressed in bytes but is a multiple of 64 bytes.
Page 180 Firewall (FW) RM0432 Bit 2 VDE: Volatile data execution 0: Volatile data segment cannot be executed if VDS = 0 1: Volatile data segment is declared executable whatever VDS bit value When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever the VDE bit value.
Page 181 RM0432 Firewall (FW) 4.4.8 Firewall register map The table below provides the Firewall register map and reset values. Table 23. Firewall register map and reset values Offset Register FW_CSSA Reset Value FW_CSL LENG Reset Value FW_NVDSSA Reset Value FW_NVDSL LENG Reset Value FW_VDSSA 0x10...
Page 182 RM0432 Power control (PWR) Power supplies The STM32L4+ Series devices require a 1.71 V to 3.6 V operating supply voltage (V Several peripherals are supplied through independent power domains: V DDIO2 . Those supplies must not be provided without a valid operating supply on...
Page 183 RM0432 Power control (PWR) When V < 2 V, V must be equal to V REF+ When V ≥ 2 V, V must be between 2 V and V REF+ can be grounded when ADC and DAC are not active. REF+ The internal voltage reference buffer supports two output voltages, which are configured with VRS bit in the VREFBUF_CSR register:...
Page 184 Power control (PWR) RM0432 Figure 10. STM32L4S9xx/L4R9xx power supply overview domain 1 x A/D converter 2 x comparators 2 x D/A converters 2 x operational amplifiers Voltage reference buffer DDUSB USB transceivers domain DDIO2 DDIO2 DDIO2 I/O ring PG[15:2] DDDSI voltage regulator CAPDSI DSI PHY...
Page 185 RM0432 Power control (PWR) ADC and DAC reference voltage To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to a separate reference voltage lower than V is the highest voltage, REF+ REF+ represented by the full scale value, for an analog input (ADC) or output (DAC) signal. can be provided either by an external reference of by an internal buffered voltage REF+ reference (VREFBUF).
Page 186 Power control (PWR) RM0432 pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin. • VSSDSI pin is an isolated supply ground used for DSI sub-system. If DSI functionality is not used at all, then: • VDDDSI pin must be connected to global VDD. •...
Page 187 RM0432 Power control (PWR) When the backup domain is supplied by V (analog switch connected to V because is not present), the following functions are available: • PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 46.3: RTC functional description)
Page 188 Power control (PWR) RM0432 preserved (depending on RRS[1:0] bits in the PWR_CR3 register). The main regulator (MR) is off and the low-power regulator (LPR) provides the supply only to SRAM2. The core, digital peripherals (except Standby circuitry and backup domain) and SRAM1 are powered off.
Page 189 RM0432 Power control (PWR) There are two possible states: • Connected: Switch is closed so SMPS powers VDD12 • Disconnected: Switch is open and VDD12 is disconnected from SMPS output Proper software management through GPIOs to enable/disable SMPS and to connect/disconnect SMPS through the switch, is required to conform with the rules described below.
Page 190 Power control (PWR) RM0432 In Range1, the main regulator operates in two modes following the R1MODE bit in the PWR_CR5 register: • Main regulator Range 1 normal mode: provides a typical output voltage at 1.2 V. It is used when the system clock frequency is up to 80 MHz. The Flash access time for read access is minimum, write and erase operations are possible.
Page 191 RM0432 Power control (PWR) 1. Program the VOS bits to “01” in the PWR_CR1 register. 2. Wait until the VOSF flag is cleared in the PWR_SR2 register. 3. Adjust number of wait states according new frequency target in Range 1 (LATENCY bits in the FLASH_ACR).
Page 192 Power control (PWR) RM0432 Start SMPS converter (if not always enabled by HW). Check that SMPS converter output is at the correct level, like 1.25 V ≤ VDD12 < 1.32 V. Connect VDD12 to external SMPS converter through the switch. •...
Page 193 RM0432 Power control (PWR) Figure 12. Brown-out reset waveform (rising edge) BOR0 hysteresis (falling edge) BOR0 Temporization RSTTEMPO Reset MS31444V5 1. The reset temporization t is present only for the BOR lowest threshold (V RSTTEMPO BOR0 5.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the...
Page 194 Power control (PWR) RM0432 5.2.3 Peripheral Voltage Monitoring (PVM) Only V is monitored by default, as it is the only supply required for all system-related functions. The other supplies (V and V ) can be independent from V DDIO2 DDUSB and can be monitored with four Peripheral Voltage Monitoring (PVM).
Page 195 RM0432 Power control (PWR) If V is independent from V DDIO2 Enable the PVM2 by setting PVME2 bit in the Power control register 2 (PWR_CR2). Wait for the PVM2 wakeup time Wait until PVMO2 bit is cleared in the Power status register 2 (PWR_SR2).
Page 196 Power control (PWR) RM0432 PWR_CR1 register (default setting). Stop 2 mode with SRAM3 retention when the RRSTP bit is set in PWR_CR1 register. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, which allows the fastest wakeup time but with much higher consumption.
Page 197 RM0432 Power control (PWR) Figure 14. Low-power modes possible transitions Low power sleep mode Sleep mode Low power run mode Shutdown mode Run mode Standby mode Stop 1 mode Stop 0 mode Stop 2 mode MS33361V2 RM0432 Rev 6 197/2301...
Page 198 Power control (PWR) RM0432 Table 26. Low-power mode summary Voltage Wakeup Wakeup regulators Mode name Entry Effect on clocks source system clock WFI or Return Sleep CPU clock OFF Same as before Any interrupt from ISR entering Sleep (Sleep-now or no effect on other clocks mode Sleep-on-exit)
Page 199 RM0432 Power control (PWR) Table 26. Low-power mode summary (continued) Voltage Wakeup Wakeup regulators Mode name Entry Effect on clocks source system clock LPMS=”000” + SLEEPDEEP bit Stop 0 + WFI or Return HSI16 when from ISR or WFE Any EXTI line STOPWUCK=1 in LPMS=”001”...
Page 200 Power control (PWR) RM0432 Table 27. Functionalities depending on the working mode Stop 0/1 Stop 2 Standby Shutdown Peripheral Sleep VBAT Flash memory (2 Mbytes) SRAM1 (192 Kbytes for STM32L4Rxxx and STM32L4Sxxx) (128 Kbytes for STM32L4P5xx and STM32L4Q5xx) SRAM2 (64 Kbytes) SRAM3 (384 Kbytes for STM32L4Rxxx and...
Page 201 RM0432 Power control (PWR) Table 27. Functionalities depending on the working mode (continued) Stop 0/1 Stop 2 Standby Shutdown Peripheral Sleep VBAT Multi-speed internal (MSI) Clock security system (CSS) Clock security system on RTC / Auto wakeup Number of RTC tamper pins DCMI/PSSI LCD-TFT GFXMMU...
Page 202 Power control (PWR) RM0432 Table 27. Functionalities depending on the working mode (continued) Stop 0/1 Stop 2 Standby Shutdown Peripheral Sleep VBAT Temperature sensor Timers (TIMx) Low-power timer 1 (LPTIM1) Low-power timer 2 (LPTIM2) Independent watchdog (IWDG) Window watchdog (WWDG) SysTick timer Touch sensing controller (TSC)
Page 203 RM0432 Power control (PWR) 10. Voltage scaling Range 1 only. 11. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode. 12. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 13. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
Page 204 Power control (PWR) RM0432 Optional: Jump into the SRAM and power-down the Flash by setting the RUN_PD bit in Flash access control register (FLASH_ACR). Decrease the system clock frequency below 2 MHz. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register. Refer to Table 28: Low-power run on how to enter the Low-power run mode.
Page 205 RM0432 Power control (PWR) IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU. ® - When SEVONPEND = 1 in the Cortex -M4 System Control register.
Page 206 Power control (PWR) RM0432 Table 29. Sleep Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 – No interrupt (for WFI) or event (for WFE) is pending ® Refer to the Cortex -M4 System Control register.
Page 207 RM0432 Power control (PWR) Table 30. Low-power sleep Low-power sleep-now Description mode Low-power sleep mode is entered from the Low-power run mode. WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 – No interrupt (for WFI) or event (for WFE) is pending ®...
Page 208 Power control (PWR) RM0432 Refer to Table 31: Stop 0 mode for details on how to enter the Stop 0 mode. If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB access is finished.
Page 209 RM0432 Power control (PWR) Table 31. Stop 0 mode Stop 0 mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 210 Power control (PWR) RM0432 Table 32. Stop 1 mode Stop 1 mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 211 RM0432 Power control (PWR) Note: The comparators outputs, the LPUART outputs and the LPTIM1 outputs are forced to low speed (OSPEEDy=00) during the Stop 2 mode. I/O states in Stop 2 mode In the Stop 2 mode, all I/O pins keep the same state as in the Run mode. Entering Stop 2 mode The Stop 2 mode is entered according Section : Entering low-power...
Page 212 Power control (PWR) RM0432 Refer to Table 33: Stop 2 mode for details on how to exit Stop 2 mode. When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is selected as system clock if the bit STOPWUCK is set in Clock configuration register (RCC_CFGR).
Page 213 RM0432 Power control (PWR) SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are also switched off. SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 9).
Page 214 Power control (PWR) RM0432 Refer to Table 34: Standby mode for more details on how to exit Standby mode. When exiting Standby mode, I/O’s that were configured with pull-up or pull-down during Standby through registers PWR_PUCRx or PWR_PDCRx will keep this configuration upon exiting Standby mode until the bit APC of PWR_CR3 register has been cleared.
Page 215 RM0432 Power control (PWR) 5.3.10 Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. It is based on the Deepsleep mode, with the voltage regulator disabled. The V domain is consequently CORE powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
Page 216 Power control (PWR) RM0432 will be configured in floating state or to their pull-up pull-down reset value (for some I/Os listed in Section 8.3.1: General-purpose I/O (GPIO)). Table 35. Shutdown mode Shutdown mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ®...
Page 217 RM0432 Power control (PWR) PWR registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 5.4.1 Power control register 1 (PWR_CR1) Address offset: 0x00 Reset value: 0x0000 0200 (This register is reset after wakeup from Standby mode) Res.
Page 218 Power control (PWR) RM0432 Bit 4 RRSTP: SRAM3 retention in Stop 2 mode 0: SRAM3 is powered off in Stop 2 mode (SRAM3 content is lost) 1: SRAM3 is powered in Stop 2 mode (RAM3 content is kept). Bit 3 Reserved, must be kept at reset value. Bits 2:0 LPMS[2:0]: Low-power mode selection These bits select the low-power mode entered when CPU enters the Deepsleep mode.
Page 219 RM0432 Power control (PWR) Bit 6 PVME3: Peripheral voltage monitoring 3 enable: vs. 1.62V 0: PVM3 ( monitoring vs. 1.62V threshold) disable. 1: PVM3 ( monitoring vs. 1.62V threshold) enable. Bit 5 PVME2: Peripheral voltage monitoring 2 enable: vs. 0.9V DDIO2 0: PVM2 ( monitoring vs.
Page 220 Power control (PWR) RM0432 Bits 31:16 Reserved, must be kept at reset value. Bit 15 EIWUL: Enable internal wakeup line 0: Internal wakeup line disable. 1: Internal wakeup line enable. Bits 14:13 Reserved, must be kept at reset value. Bit 12 DSIPDEN: Enable Pull-down activation on DSI pins 1: Pull-Down is enabled on DSI pins.
Page 221 RM0432 Power control (PWR) Bit 2 EWUP3: Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register.
Page 222 Power control (PWR) RM0432 Bit 4 WP5: Wakeup pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5 0: Detection on high level (rising edge) 1: Detection on low level (falling edge) Bit 3 WP4: Wakeup pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4 0: Detection on high level (rising edge)
Page 223 RM0432 Power control (PWR) Bit 13 EXT_SMPS_RDY: External SMPS ready This bit informs the state of regulator transition from Range 1 to Range 2 0: Internal regulator not ready in Range 2, the external SMPS cannot be connected 1: Internal regulator ready in Range 2, the external SMPS can be connected Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices.
Page 224 Power control (PWR) RM0432 Bits 31:16 Reserved, must be kept at reset value. Bit 15 PVMO4: Peripheral voltage monitoring output: V vs. 2.2 V 0: V voltage is above PVM4 threshold (around 2.2 V). 1: V voltage is below PVM4 threshold (around 2.2 V). Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0).
Page 225 RM0432 Power control (PWR) Reset value: 0x0000 0000 Access: 3 additional APB cycles are needed to write this register vs. a standard APB write. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CWUF CWUF CWUF...
Page 226 Power control (PWR) RM0432 Bits 31:16 Reserved, must be kept at reset value. Bit 15 PU15: Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. If the corresponding PD15 bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority.
Page 227 RM0432 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
Page 228 Power control (PWR) RM0432 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register.
Page 229 RM0432 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register.
Page 230 Power control (PWR) RM0432 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port E pull-up bit y (y=0..15) When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register.
Page 231 RM0432 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register.
Page 232 Power control (PWR) RM0432 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register.
Page 233 RM0432 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register.
Page 234 Power control (PWR) RM0432 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 11:0 PUy: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register.
Page 235 RM0432 Power control (PWR) Bits 31:9 Reserved, must be kept at reset value. Bit 8 R1MODE: Main regulator Range 1 mode This bit is only valid for the main regulator in Range 1 and has no effect on Range 2. It is recommended to reset this bit when the system frequency is greater than 80 MHz.
Page 236 Power control (PWR) RM0432 5.4.27 PWR register map and reset value table Table 36. PWR register map and reset values Offset Register LPMS PWR_CR1 [1:0] [2:0] 0x000 Reset value PWR_CR2 PLS [2:0] 0x004 Reset value PWR_CR3 0x008 Reset value PWR_CR4 0x00C Reset value PWR_SR1...
Page 237 RM0432 Power control (PWR) Table 36. PWR register map and reset values (continued) Offset Register PWR_PUCRD 0x038 Reset value PWR_PDCRD 0x03C Reset value PWR_PUCRE 0x040 Reset value PWR_PDCRE 0x044 Reset value PWR_PUCRF 0x048 Reset value PWR_PDCRF 0x04C Reset value PWR_PUCRG 0x050 Reset value PWR_PDCRG...
Page 238 Reset and clock control (RCC) RM0432 Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and backup domain reset. 6.1.1 Power reset A power reset is generated when one of the following events occurs: a Brown-out reset (BOR).
Page 239 -M4 Application Interrupt and Reset Control Register must be set to force a software reset on the device (refer to the STM32F3, STM32F4, ® STM32L4 and STM32L4+ Series Cortex -M4 (PM0214)). Low-power mode security reset To prevent that critical applications mistakenly enter a low-power mode, two low-power mode security resets are available.
Page 240 Reset and clock control (RCC) RM0432 Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). or V power on, if both supplies have previously been powered off. A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and the RCC Backup domain control register.
Page 241 RM0432 Reset and clock control (RCC) All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except: • The 48 MHz clock, used for USB OTG FS, SDMMC and RNG. This clock is derived (selected by software) from one of the four following sources: –...
Page 242 (HCLK), configurable in the SysTick Control and Status Register. ® FCLK acts as Cortex -M4 free-running clock. For more details refer to the STM32F3, ® STM32F4, STM32L4 and STM32L4+ Series Cortex -M4 programming manual (PM0214). 242/2301 RM0432 Rev 6...
Page 243 RM0432 Reset and clock control (RCC) Figure 16. Clock tree for STM32L4Rxxx and STM32L4Sxxx devices to IWDG LSI RC 32 kHz LSCO to RTC OSC32_OUT LSE OSC 32.768 kHz OSC32_IN to PWR to AHB bus, core, memory and DMA HSI16 / 1→16 HCLK FCLK Cortex free running clock...
Page 244 Reset and clock control (RCC) RM0432 1. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. 2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4).
Page 245 RM0432 Reset and clock control (RCC) Figure 18. Clock tree for STM32L4P5xx and STM32L4Q5xx devices to IWDG LSI RC 32 kHz LSCO to RTC OSC32_OUT LSE OSC 32.768 kHz OSC32_IN to PWR to AHB bus, core, memory and DMA HSI16 / 1→16 HCLK FCLK Cortex free running clock...
Page 246 Reset and clock control (RCC) RM0432 6.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time.
Page 247 Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 248 The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the...
Page 249 RM0432 Reset and clock control (RCC) can use the USB SOF signal, the LSE or an external signal to automatically and quickly adjust the oscillator frequency on-fly. It is disabled as soon as the system enters Stop or Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its default frequency which is subject to manufacturing process variations.
Page 250 Reset and clock control (RCC) RM0432 The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN, PLLSAI1PEN, PLLSAI1QEN, PLLSAI1REN, PLLSAI2PEN and PLLSAI2REN) can be modified at any time without stopping the corresponding PLL. PLLREN cannot be cleared if PLLCLK is used as system clock.
Page 251 RM0432 Reset and clock control (RCC) 6.2.8 System clock (SYSCLK) selection Four different clock sources can be used to drive the system clock (SYSCLK): • MSI oscillator • HSI16 oscillator • HSE oscillator • The system clock maximum frequency is 120 MHz. After a system reset, the MSI oscillator, at 4 MHz, is selected as system clock.
Page 252 Reset and clock control (RCC) RM0432 6.2.10 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1/TIM8 and TIM15/16/17) and an interrupt is generated to inform the software about the failure (Clock...
Page 253 RM0432 Reset and clock control (RCC) 6.2.12 ADC clock The ADC clock is derived from the system clock, or from the PLLSAI1 output. It can reach 120 MHz and can be divided by the following prescalers values: 1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is asynchronous to the AHB clock.
Page 254 Reset and clock control (RCC) RM0432 6.2.16 Clock-out capability • The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. One of eight clock signals can be selected as the MCO clock. – –...
Page 255 RM0432 Reset and clock control (RCC) The input capture channel of the Timer 15 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP bit in the TIM15_OR register. The possibilities are the following ones: •...
Page 256 Reset and clock control (RCC) RM0432 The input capture channel of the Timer 17 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register. The possibilities are the following ones: •...
Page 257 RM0432 Reset and clock control (RCC) 6.2.18 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR, RCC_APBxENRy registers. When the peripheral clock is not active, the peripheral registers read or write accesses are not supported.
Page 258 Reset and clock control (RCC) RM0432 RCC registers 6.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 0063. HSEBYP is not affected by reset. Access: no wait state, word, half-word and byte access PLLSAI PLLSAI PLLSAI PLLSAI PLLRD Res.
Page 259 RM0432 Reset and clock control (RCC) Bit 19 CSSON: Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected.
Page 260 Reset and clock control (RCC) RM0432 Bit 8 HSION: HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.
Page 261 RM0432 Reset and clock control (RCC) Bit 0 MSION: MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock.
Page 262 Reset and clock control (RCC) RM0432 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers values update is on going.
Page 263 RM0432 Reset and clock control (RCC) Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB2 clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 10:8 PPRE1[2:0]:APB low-speed prescaler (APB1)
Page 264 Reset and clock control (RCC) RM0432 6.4.4 PLL configuration register (RCC_PLLCFGR) Address offset: 0x0C Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLL clock outputs according to the formulas: •...
Page 265 RM0432 Reset and clock control (RCC) Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL48M1CLK (48 MHz clock). Set and cleared by software to control the frequency of the main PLL output clock PLL48M1CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These bits can be written only if PLL is disabled.
Page 266 Reset and clock control (RCC) RM0432 Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 127 0000000: PLLN = 0 wrong configuration 0000001: PLLN = 1 wrong configuration 0000111: PLLN = 7 wrong configuration...
Page 267 RM0432 Reset and clock control (RCC) • f(PLLSAI1_R) = f(VCOSAI1 clock) / PLLSAI1R PLLSAI PLLSAI PLLSAI PLLSAI PLLSAI1PDIV[4:0] PLLSAI1R[1:0] Res. PLLSAI1Q[1:0] Res. Res. 1REN 1QEN 1PEN Res. PLLSAI1N[6:0] PLLSAI1M[3:0] Res. Res. Res. Res. Bits 31:27 PLLSAI1PDIV[4:0]: PLLSAI1 division factor for PLLSAI1CLK Set and cleared by software to control the SAI1 or SAI2 clock frequency.
Page 268 Reset and clock control (RCC) RM0432 Bit 20 PLLSAI1QEN: PLLSAI1 PLL48M2CLK output enable Set and reset by software to enable the PLL48M2CLK output of the PLLSAI1. In order to save power, when the PLL48M2CLK output of the PLLSAI1 is not used, the value of PLLSAI1QEN should be 0.
Page 269 RM0432 Reset and clock control (RCC) Bits 14:8 PLLSAI1N[6:0]: PLLSAI1 multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLLSAI1 is disabled. VCOSAI1 output frequency = VCOSAI1 input frequency x PLLSAI1N with 8 =<...
Page 270 Reset and clock control (RCC) RM0432 6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR) Address offset: 0x14 Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLLSAI2 clock outputs according to the formulas: •...
Page 271 RM0432 Reset and clock control (RCC) Bits 22:21 PLLSAI2Q[1:0]: PLLSAI2 PLLDSICLK output enable. Set and cleared by software to control the frequency of the DSI clock. These bits can be written only if PLLSAI2 is disabled. PLLDSICLK output clock frequency = VCOSAI2 frequency / PLLSAI2Q with PLLSAI2Q = 2, 4, 6, or 8 00: PLLSAI2Q = 2 01: PLLSAI2Q = 4...
Page 272 Reset and clock control (RCC) RM0432 Bits 14:8 PLLSAI2N[6:0]: PLLSAI2 multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLLSAI2 is disabled. VCOSAI2 output frequency = VCOSAI2 input frequency x PLLSAI2N with 8 =<...
Page 273 RM0432 Reset and clock control (RCC) Bits 31:11 Reserved, must be kept at reset value. Bit 10 HSI48RDYIE: HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. 0: HSI48 ready interrupt disabled 1: HSI48 ready interrupt enabled Bit 9 LSECSSIE: LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system...
Page 274 Reset and clock control (RCC) RM0432 Bit 2 MSIRDYIE: MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. 0: MSI ready interrupt disabled 1: MSI ready interrupt enabled Bit 1 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
Page 275 RM0432 Reset and clock control (RCC) Bit 7 PLLSAI2RDYF: PLLSAI2 ready interrupt flag Set by hardware when the PLLSAI2 locks and PLLSAI2RDYDIE is set. Cleared by software setting the PLLSAI2RDYC bit. 0: No clock ready interrupt caused by PLLSAI2 lock 1: Clock ready interrupt caused by PLLSAI2 lock Bit 6 PLLSAI1RDYF: PLLSAI1 ready interrupt flag Set by hardware when the PLLSAI1 locks and PLLSAI1RDYDIE is set.
Page 276 Reset and clock control (RCC) RM0432 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HSI48 LSECS PLLSAI PLLSAI HSER HSIRD MSIRD LSERD LSIRDY Res.
Page 277 RM0432 Reset and clock control (RCC) Bit 2 MSIRDYC: MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag. 0: No effect 1: MSIRDYF cleared Bit 1 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 0 LSIRDYC: LSI ready interrupt clear...
Page 278 Reset and clock control (RCC) RM0432 Bits 11:9 Reserved, must be kept at reset value. Bit 8 FLASHRST: Flash memory interface reset Set and cleared by software. This bit can be activated only when the Flash memory is in power down mode. 0: No effect 1: Reset Flash memory interface Bits 7:3 Reserved, must be kept at reset value.
Page 279 RM0432 Reset and clock control (RCC) Bit 20 OSPIMRST: OctoSPI IO manager reset Set and cleared by software. 0: No effect 1: Reset OctoSPI IO manager Bit 19 Reserved, must be kept at reset value. Bit 18 RNGRST: Random number generator reset Set and cleared by software.
Page 280 Reset and clock control (RCC) RM0432 Bit 6 GPIOGRST: IO port G reset Set and cleared by software. 0: No effect 1: Reset IO port G Bit 5 GPIOFRST: IO port F reset Set and cleared by software. 0: No effect 1: Reset IO port F Bit 4 GPIOERST: IO port E reset Set and cleared by software.
Page 281 RM0432 Reset and clock control (RCC) Bits 31:10 Reserved, must be kept at reset value. Bit 9 OSPI2RST: OctoSPI2 memory interface reset Set and cleared by software. 0: No effect 1: Reset OctoSPI2 Bit 8 OSPI1RST: OctoSPI1 memory interface reset Set and cleared by software.
Page 282 Reset and clock control (RCC) RM0432 Bit 27:26 Reserved, must be kept at reset value. Bit 25 CAN1RST: CAN1 reset Set and reset by software. 0: No effect 1: Reset the CAN1 Bit 24 CRSRST: CRS reset Set and cleared by software. 0: No effect 1: Reset the CRS Bit 23 I2C3RST: I2C3 reset...
Page 283 RM0432 Reset and clock control (RCC) Bits 13:6 Reserved, must be kept at reset value. Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software. 0: No effect 1: Reset TIM6 Bit 3 TIM5RST: TIM5 timer reset...
Page 284 Reset and clock control (RCC) RM0432 Bits 4:2 Reserved, must be kept at reset value. Bit 1 I2C4RST: I2C4 reset Set and cleared by software 0: No effect 1: Reset I2C4 Bit 0 LPUART1RST: Low-power UART 1 reset Set and cleared by software. 0: No effect 1: Reset LPUART1 6.4.15...
Page 285 RM0432 Reset and clock control (RCC) Bit 21 SAI1RST: Serial audio interface 1 (SAI1) reset Set and cleared by software. 0: No effect 1: Reset SAI1 Bits 20:19 Reserved, must be kept at reset value. Bit 18 TIM17RST: TIM17 timer reset Set and cleared by software.
Page 286 Reset and clock control (RCC) RM0432 6.4.16 AHB1 peripheral clock enable register (RCC_AHB1ENR) Address offset: 0x48 Reset value: 0x0000 0100 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 287 RM0432 Reset and clock control (RCC) Bit 2 DMAMUX1EN: DMAMUX1 clock enable Set and reset by software. 0: DMAMUX1 clock disabled 1: DMAMUX1 clock enabled Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disable 1: DMA2 clock enable Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software.
Page 288 Reset and clock control (RCC) RM0432 Bit 18 RNGEN: Random Number Generator clock enable Set and cleared by software. 0: Random Number Generator clock disabled 1: Random Number Generator clock enabled Bit 17 HASHEN: HASH clock enable Set and cleared by software 0: HASH clock disabled 1: HASH clock enabled Bit 16 AESEN: AES accelerator clock enable...
Page 289 RM0432 Reset and clock control (RCC) Bit 4 GPIOEEN: IO port E clock enable Set and cleared by software. 0: IO port E clock disabled 1: IO port E clock enabled Bit 3 GPIODEN: IO port D clock enable Set and cleared by software. 0: IO port D clock disabled 1: IO port D clock enabled Bit 2 GPIOCEN: IO port C clock enable...
Page 290 Reset and clock control (RCC) RM0432 Bit 8 OSPI1EN: OctoSPI1 memory interface clock enable Set and cleared by software. 0: OctoSPI1 clock disable 1: OctoSPI1 clock enable Bits 7:1 Reserved, must be kept at reset value. Bit 0 FMCEN: Flexible memory controller clock enable Set and cleared by software.
Page 291 RM0432 Reset and clock control (RCC) Bit 25 CAN1EN: CAN1 clock enable Set and cleared by software. 0: CAN1 clock disabled 1: CAN1 clock enabled Bit 24 CRSEN: Clock Recovery System clock enable Set and cleared by software 0: CRS clock disabled 1: CRS clock enabled Bit 23 I2C3EN: I2C3 clock enable Set and cleared by software.
Page 292 Reset and clock control (RCC) RM0432 Bit 11 WWDGEN: Window watchdog clock enable Set by software to enable the window watchdog clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bit 10 RTCAPBEN: RTC APB clock enable...
Page 293 RM0432 Reset and clock control (RCC) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM2 LPUAR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C4EN T1EN Bits 31:6 Reserved, must be kept at reset value. Bit 5 LPTIM2EN Low power timer 2 clock enable Set and cleared by software.
Page 294 Reset and clock control (RCC) RM0432 6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x60 Reset value: 0x0000 0000 Access: word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 295 RM0432 Reset and clock control (RCC) Bit 17 TIM16EN: TIM16 timer clock enable Set and cleared by software. 0: TIM16 timer clock disabled 1: TIM16 timer clock enabled Bit 16 TIM15EN: TIM15 timer clock enable Set and cleared by software. 0: TIM15 timer clock disabled 1: TIM15 timer clock enabled Bit 15 Reserved, must be kept at reset value.
Page 296 Reset and clock control (RCC) RM0432 GFXM DMA2D TSCS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MUSM SMEN DMAM SRAM1 FLASH DMA2S DMA1 Res. Res. Res. CRCSMEN Res. Res. Res. Res. Res. Res. Res. UX1S SMEN SMEN...
Page 297 RM0432 Reset and clock control (RCC) Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during Sleep and Stop modes. Set and cleared by software. 0: DMAMUX1 clocks disabled by the clock gating during Sleep and Stop modes 1: DMAMUX1 clocks enabled by the clock gating during Sleep and Stop modes Bit 1 DMA2SMEN: DMA2 clocks enable during Sleep and Stop modes Set and cleared by software during Sleep mode.
Page 298 Reset and clock control (RCC) RM0432 Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes Set and cleared by software. 0: Random Number Generator clocks disabled by the clock gating during Sleep and Stop modes 1: Random Number Generator clocks enabled by the clock gating during Sleep and Stop modes Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes Set and cleared by software...
Page 299 RM0432 Reset and clock control (RCC) Bit 7 GPIOHSMEN: IO port H clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port H clocks disabled by the clock gating during Sleep and Stop modes 1: IO port H clocks enabled by the clock gating during Sleep and Stop modes Bit 6 GPIOGSMEN: IO port G clocks enable during Sleep and Stop modes Set and cleared by software.
Page 300 Reset and clock control (RCC) RM0432 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OCTOS OSPI1S FMCS Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:10 Reserved, must be kept at reset value. Bit 9 OCTOSPI2: OctoSPI2 memory interface clocks enable during Sleep and Stop modes Set and cleared by software.
Page 301 RM0432 Reset and clock control (RCC) Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: OPAMP interface clocks disabled by the clock gating during Sleep and Stop modes 1: OPAMP interface clocks enabled by the clock gating during Sleep and Stop modes Bit 29 DAC1SMEN: DAC1 interface clocks enable during Sleep and Stop modes Set and cleared by software.
Page 302 Reset and clock control (RCC) RM0432 Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART2 clocks disabled by the clock gating during Sleep and Stop modes 1: USART2 clocks enabled by the clock gating during Sleep and Stop modes Bit 16 Reserved, must be kept at reset value.
Page 303 RM0432 Reset and clock control (RCC) Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM2 clocks disabled by the clock gating during Sleep and Stop modes 1: TIM2 clocks enabled by the clock gating during Sleep and Stop modes 1.
Page 304 Reset and clock control (RCC) RM0432 6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) Address: 0x80 Reset value: 0x0D67 7801 Access: word, half-word and byte access DFSD .DSISM LTDCS SAI2S SAI1S TIM17S TIM16S TIM15S Res. Res. Res.
Page 305 RM0432 Reset and clock control (RCC) Bit 17 TIM16SMEN: TIM16 timer clocks enable during Sleep and Stop modes Set and cleared by software. 0: TIM16 timer clocks disabled by the clock gating during Sleep and Stop modes 1: TIM16 timer clocks enabled by the clock gating during Sleep and Stop modes Bit 16 TIM15SMEN: TIM15 timer clocks enable during Sleep and Stop modes Set and cleared by software.
Page 306 Reset and clock control (RCC) RM0432 Res. Res. ADCSEL[1:0] CLK48SEL[1:0] Res. LPTIM2SEL[1:0] LPTIM1SEL[1:0 I2C3SEL[1:0] LPUART1SEL[1: USART3SEL[1:0 USART1SEL[1:0 I2C2SEL[1:0] I2C1SEL[1:0] UART5SEL[1:0] UART4SEL[1:0] USART2SEL[1:0] Bit 31 Reserved, must be kept at reset value. Bit 30 Reserved, must be kept at reset value. Bits 29:28 ADCSEL[1:0]: ADCs clock source selection These bits are set and cleared by software to select the clock source used by the ADC interface.
Page 307 RM0432 Reset and clock control (RCC) Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection These bits are set and cleared by software to select the I2C2 clock source. 00: PCLK selected as I2C2 clock 01: System clock (SYSCLK) selected as I2C2 clock 10: HSI16 clock selected as I2C2 clock 11: Reserved Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection...
Page 308 Reset and clock control (RCC) RM0432 6.4.29 Backup domain control register (RCC_BDCR) Address offset: 0x90 Reset value: 0x0000 0000, reset by Backup domain Reset, except LSCOSEL, LSCOEN and BDRST which are reset only by Backup domain power-on reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register.
Page 309 RM0432 Reset and clock control (RCC) Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set).
Page 310 Reset and clock control (RCC) RM0432 Bit 2 LSEBYP: LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0). 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready...
Page 311 RM0432 Reset and clock control (RCC) Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 BORRSTF: BOR flag Set by hardware when a BOR occurs.
Page 312 Reset and clock control (RCC) RM0432 Bit 4 LSIPREDIV: Internal low-speed oscillator predivided by 128 Set and reset by software. This bit is used to enable the internal clock divider (/128) of the LSI clock. The software has to disable the LSI (LSION=0 and LSIRDY=0) before to change this bit.
Page 313 RM0432 Reset and clock control (RCC) Bits 6:2 Reserved, must be kept at reset value Bit 1 HSI48RDY: HSI48 clock ready flag Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON.
Page 314 Reset and clock control (RCC) RM0432 Bit 14 SDMMCSEL: SDMMC clock selection Set and reset by software. This bit allows to select the SDMMC kernel clock source between PLLP clock (PLLSAI3CLK) or clock from internal multiplexor. It is recommended to change this bit only after reset and before enabling the SDMMC module. 0: 48 MHz clock is selected as SDMMC kernel clock 1: PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode).
Page 315 RM0432 Reset and clock control (RCC) Bits 4:3 ADFSDMSEL: Digital filter for sigma delta modulator audio clock source selection Set and reset by software. 00: SAI1clock selected as DFSDM audio clock 01: HSI clock selected as DFSDM audio clock 10: MSI clock selected as DFSDM audio clock 11: reserved Bit 2 DFSDMSEL: Digital filter for sigma delta modulator kernel clock source selection Set and reset by software.
Page 316 Reset and clock control (RCC) RM0432 Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 OCTOSPI2_DLY: Delay sampling configuration on OCTOSPI2 to be used for internal sampling clock (called feedback clock) or for DQS data strobe. Set and reset by software. 0000: 1 unitary delay 0001: 2 unitary delays 0010: 3 unitary delays...
Page 317 RM0432 Reset and clock control (RCC) Table 38. RCC register map and reset values (continued) Off- Register RCC_ PLLSAI1PDI PLLSAI1N SAI1 SAI1 PLLSAI1M PLLSAI1 [3:0] [6:0] 0x10 [4:0] CFGR [1:0] [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reset value SAI2...
Page 318 Reset and clock control (RCC) RM0432 Table 38. RCC register map and reset values (continued) Off- Register RCC_ AHB3RSTR 0x30 Reset value RCC_ APB1RSTR1 0x38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value RCC_ APB1RSTR2...
Page 319 RM0432 Reset and clock control (RCC) Table 38. RCC register map and reset values (continued) Off- Register RCC_ APB1ENR2 0x5C Reset value RCC_ APB2ENR 0x60 0 0 0 0 0 0 0 Reset value RCC_ AHB1SMENR 0x68 1 1 1 1 1 1 Reset value RCC_...
Page 320 Reset and clock control (RCC) RM0432 Table 38. RCC register map and reset values (continued) Off- Register RCC_ APB2SMENR 0x80 1 1 1 1 1 1 1 Reset value RCC_CCIPR 0x88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value RCC_BDCR 0x90...
Page 321 RM0432 Clock recovery system (CRS) Clock recovery system (CRS) Introduction The clock recovery system (CRS) is an advanced digital controller acting on the internal fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means for oscillator output frequency evaluation, based on comparison with a selectable synchronization signal.
Page 322 Clock recovery system (CRS) RM0432 CRS functional description 7.4.1 CRS block diagram Figure 23. CRS block diagram CRS_SYNC GPIO SYNCSRC SWSYNC OSC32_IN SYNC divider (/1, /2, /4,…, /128) OSC32_OUT SYNC USB_DP FELIM USB_DM TRIM FEDIR FECAP 16-bit counter RC 48 MHz RELOAD HSI48 To peripherals...
Page 323 RM0432 Clock recovery system (CRS) 7.4.3 Frequency error measurement The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD value on each SYNC event. It starts counting down till it reaches the zero value, where the ESYNC (expected synchronization) event is generated.
Page 324 Clock recovery system (CRS) RM0432 7.4.4 Frequency error evaluation and automatic trimming The measured frequency error is evaluated by comparing its value with a set of limits: – TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register –...
Page 325 RM0432 Clock recovery system (CRS) FELIM value The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics and its typical trimming step size. The optimal value corresponds to half of the trimming step size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be used: FELIM = (f ) * STEP[%] / 100% / 2...
Page 326 Clock recovery system (CRS) RM0432 CRS registers Refer to Section 1.2 on page 84 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed only by words (32-bit). 7.7.1 CRS control register (CRS_CR) Address offset: 0x00 Reset value: 0x0000 X000 (X=4 for products supporting 7-bit TRIM width, otherwise X=2) Res.
Page 327 RM0432 Clock recovery system (CRS) Bit 4 Reserved, must be kept at reset value. Bit 3 ESYNCIE: Expected SYNC interrupt enable 0: Expected SYNC (ESYNCF) interrupt disabled 1: Expected SYNC (ESYNCF) interrupt enabled Bit 2 ERRIE: Synchronization or trimming error interrupt enable 0: Synchronization or trimming error (ERRF) interrupt disabled 1: Synchronization or trimming error (ERRF) interrupt enabled Bit 1 SYNCWARNIE: SYNC warning interrupt enable...
Page 328 Clock recovery system (CRS) RM0432 Bits 26:24 SYNCDIV[2:0]: SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. 000: SYNC not divided (default) 001: SYNC divided by 2 010: SYNC divided by 4 011: SYNC divided by 8 100: SYNC divided by 16 101: SYNC divided by 32...
Page 329 RM0432 Clock recovery system (CRS) Bit 9 SYNCMISS: SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action has to be taken.
Page 330 Clock recovery system (CRS) RM0432 7.7.4 CRS interrupt flag clear register (CRS_ICR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYNC SYNC Res. Res. Res. Res.
Page 331 RM0432 Clock recovery system (CRS) 7.7.5 CRS register map Table 42. CRS register map and reset values Offset Register TRIM[5:0] CRS_CR 0x00 Reset value SYNC SYNC CRS_CFGR FELIM[7:0] RELOAD[15:0] 0x04 [1:0] [2:0] Reset value CRS_ISR FECAP[15:0] 0x08 Reset value CRS_ICR 0x0C Reset value 1.
Page 332 General-purpose I/Os (GPIO) RM0432 General-purpose I/Os (GPIO) Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 333 RM0432 General-purpose I/Os (GPIO) Figure 25 Figure 26 show the basic structures of a standard and a 5-Volt tolerant I/O port bit, respectively. Table 43 gives the possible port bit configurations. Figure 25. Basic structure of an I/O port bit Analog To on-chip peripheral...
Page 334 General-purpose I/Os (GPIO) RM0432 Table 43. Port bit configuration table MODE(i) OSPEED(i) PUPD(i) OTYPER(i) I/O configuration [1:0] [1:0] [1:0] GP output GP output PP + PU GP output PP + PD Reserved SPEED [1:0] GP output GP output OD + PU GP output OD + PD Reserved (GP output OD)
Page 335 RM0432 General-purpose I/Os (GPIO) 8.3.1 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode. The debug pins are in AF pull-up/pull-down after reset: • PA15: JTDI in pull-up •...
Page 336 General-purpose I/Os (GPIO) RM0432 – Configure the desired I/O as an alternate function in the GPIOx_MODER register. • Additional functions: – For the ADC, DAC, OPAMP and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, DAC, OPAMP, and COMP registers .
Page 337 RM0432 General-purpose I/Os (GPIO) There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access. 8.3.6 GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register.
Page 338 General-purpose I/Os (GPIO) RM0432 8.3.9 Input configuration When the I/O port is programmed as input: • The output buffer is disabled • The Schmitt trigger input is activated • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register •...
Page 339 RM0432 General-purpose I/Os (GPIO) Figure 28. Output configuration Read DDIOx TTL Schmitt DDIOx trigger on/off protection Write Input driver diode pull I/O pin Output driver DDIOx on/off P-MOS protection pull down diode Output control Read/write N-MOS Push-pull or Open-drain MS31478V1 8.3.11 Alternate function configuration When the I/O port is programmed as alternate function:...
Page 340 General-purpose I/Os (GPIO) RM0432 8.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). •...
Page 341 RM0432 General-purpose I/Os (GPIO) 8.3.15 Using PH3 as GPIO PH3 may be used as boot pin (BOOT0) or as a GPIO. Depending on the nSWBOOT0 bit in the user option byte, it switches from the input mode to the analog input mode: •...
Page 342 General-purpose I/Os (GPIO) RM0432 GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The peripheral registers can be written in word, half word or byte mode. 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A to I)
Page 343 RM0432 General-purpose I/Os (GPIO) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0) These bits are written by software to configure the I/O output type. 0: Output push-pull (reset state) 1: Output open-drain 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
Page 344 General-purpose I/Os (GPIO) RM0432 Bits 31:0 PUPD[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0) These bits are written by software to configure the I/O pull-up or pull-down 00: No pull-up, pull-down 01: Pull-up 10: Pull-down 11: Reserved 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to I)
Page 345 RM0432 General-purpose I/Os (GPIO) Reset value: 0x0000 0000 BR15 BR14 BR13 BR12 BR11 BR10 BS15 BS14 BS13 BS12 BS11 BS10 Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority.
Page 346 General-purpose I/Os (GPIO) RM0432 Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 347 RM0432 General-purpose I/Os (GPIO) Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0) These bits are written by software to configure alternate function I/Os. 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6...
Page 348 General-purpose I/Os (GPIO) RM0432 Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8) These bits are written by software to configure alternate function I/Os. 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6...
Page 349 RM0432 General-purpose I/Os (GPIO) 8.4.12 GPIO register map The following table gives the GPIO register map and reset values. Table 44. GPIO register map and reset values Offset Register name GPIOA_MODER 0x00 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 GPIOB_MODER 0x00 Reset value...
Page 350 General-purpose I/Os (GPIO) RM0432 Table 44. GPIO register map and reset values (continued) Offset Register name GPIOx_ODR (where x = A..I) 0x14 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_BSRR (where x = A..I) 0x18 Reset value 0 0 0 0...
Page 351 RM0432 System configuration controller (SYSCFG) System configuration controller (SYSCFG) SYSCFG main features The STM32L4+ Series devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Remapping memory areas • Managing the external interrupt line connection to the GPIOs •...
Page 352 System configuration controller (SYSCFG) RM0432 Bits 31:9 Reserved, must be kept at reset value. Bit 8 FB_MODE: Flash Bank mode selection For 2 Mbytes devices: 0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000 and Flash Bank 2 mapped at 0x0810 0000 (and aliased at 0x0010 0000) 1: Flash Bank 2 mapped at 0x0800 0000 (and aliased @0x0000 0000 and Flash Bank 1 mapped at 0x0810 0000 (and aliased at 0x0010 0000) For 1 Mbyte devices:...
Page 353 RM0432 System configuration controller (SYSCFG) I2C_ I2C_ I2C_ I2C_ I2C4_ I2C3_ I2C2_ I2C1_ FPU_IE[5:0] Res. Res. PB9_ PB8_ PB7_ PB6_ ANAS BOOST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FWDIS WVDD rc_w0 Bits 31:26 FPU_IE[5..0]: Floating point unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable FPU_IE[4]: Input denormal interrupt enable FPU_IE[3]: Overflow interrupt enable...
Page 354 System configuration controller (SYSCFG) RM0432 Bit 16 I2C_PB6_FMP: Fast-mode Plus (Fm+) driving capability activation on PB6 This bit enables the Fm+ driving mode for PB6. 0: PB6 pin operates in standard mode. 1: Fm+ mode enabled on PB6 pin, and the Speed control is bypassed. Bits 15:10 Reserved, must be kept at reset value.
Page 355 RM0432 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI3[3:0]: EXTI 3 configuration bits These bits are written by software to select the source input for the EXTI3 external interrupt. 0000: PA[3] pin 0001: PB[3] pin 0010: PC[3] pin 0011: PD[3] pin...
Page 356 System configuration controller (SYSCFG) RM0432 9.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 357 RM0432 System configuration controller (SYSCFG) Bits 11:8 EXTI6[3:0]: EXTI 6 configuration bits These bits are written by software to select the source input for the EXTI6 external interrupt. 0000: PA[6] pin 0001: PB[6] pin 0010: PC[6] pin 0011: PD[6] pin 0100: PE[6] pin 0101: PF[6] pin 0110: PG[6] pin...
Page 358 System configuration controller (SYSCFG) RM0432 Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI11[3:0]: EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt. 0000: PA[11] pin 0001: PB[11] pin 0010: PC[11] pin 0011: PD[11] pin...
Page 359 RM0432 System configuration controller (SYSCFG) 9.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Bits 31:16 Reserved, must be kept at reset value.
Page 360 System configuration controller (SYSCFG) RM0432 Bits 11:8 EXTI14[3:0]: EXTI 14 configuration bits These bits are written by software to select the source input for the EXTI14 external interrupt. 0000: PA[14] pin 0001: PB[14] pin 0010: PC[14] pin 0011: PD[14] pin 0100: PE[14] pin 0101: PF[14] pin 0110: PG[14] pin...
Page 361 RM0432 System configuration controller (SYSCFG) Bits 31:2 Reserved, must be kept at reset value Bit 1 SRAM2BSY: SRAM2 busy by erase operation 0: No SRAM2 erase operation is on going. 1: SRAM2 erase operation is on going. Bit 0 SRAM2ER: SRAM2 Erase Setting this bit starts a hardware SRAM2 erase operation.
Page 362 System configuration controller (SYSCFG) RM0432 Bit 2 PVDL: PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
Page 363 RM0432 System configuration controller (SYSCFG) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. KEY[7:0] Bits 31:8 Reserved, must be kept at reset value Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register.
Page 364 System configuration controller (SYSCFG) RM0432 9.2.12 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 46. SYSCFG register map and reset values Offset Register SYSCFG_ MEM_ MODE MEMRMP 0x00 Reset value SYSCFG_CFGR1 FPU_IE[5..0] 0x04 Reset value EXTI3...
Page 365 RM0432 System configuration controller (SYSCFG) Refer to Section 2.2 on page 91 for the register boundary addresses. RM0432 Rev 6 365/2301...
Page 366 Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. 10.2 Connection summary (1) (2) Table 47. STM32L4+ Series peripherals interconnect matrix Destination Source TIM1 TIM8 TIM2...
Page 367 RM0432 Peripherals interconnect matrix (1) (2) Table 47. STM32L4+ Series peripherals interconnect matrix Destination Source OPAMP1 12 12 OPAMP2 12 12 DAC1 12 12 DAC2 EXTI COMP1 13 13 13 13 13 13 13 COMP2 13 13 13 13 13 13 13...
Page 368 Peripherals interconnect matrix RM0432 The modes of synchronization are detailed in: • Section 37.3.26: Timer synchronization for advanced-control timers (TIM1/TIM8) • Section 38.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2/TIM3/TIM4/TIM5) • Section 39.4.19: External trigger synchronization (TIM15 only) for general-purpose timer (TIM15) Triggering signals...
Page 369 RM0432 Peripherals interconnect matrix 10.3.3 From ADC to timer (TIM1/TIM8) Purpose ADC1 can provide trigger event through watchdog signals to advanced-control timers (TIM1/TIM8). A description of the ADC analog watchdog setting is provided in: Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx).
Page 370 Peripherals interconnect matrix RM0432 Triggering signals The output (from timer) is on signal TIMx_TRGO/TIMx_TRGO2 or TIM16_OC1. The input (on DFSDM1) is on signal DFSDM1_INTRG[0:8]. The connection between timers, EXTI and DFSDM1 is provided in Table 186: DFSDM triggers connection. Active power mode Run, Sleep, Low-power run, Low-power sleep.
Page 371 RM0432 Peripherals interconnect matrix External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin, see Section 38.4.22: TIM2 option register 1 (TIM2_OR1). Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.8 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) Purpose RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to start LPTIM counters (LPTIM1/2).
Page 372 Peripherals interconnect matrix RM0432 A description of dual ADC mode is provided in: Section 21.4.31: Dual ADC modes. Triggering signals Internal to the ADCs. Active power mode Run, Sleep, Low-power run, Low-power sleep. 10.3.11 From USB to timer (TIM2) Purpose USB (OTG_FS SOF) can generate a trigger to general-purpose timer (TIM2).
Page 373 RM0432 Peripherals interconnect matrix 10.3.13 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) Purpose Comparators (COMP1/COMP2) output values can be connected to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) input captures or TIMx_ETR signals. The connection to ETR is described in Section 37.3.4: External trigger input. Comparators (COMP1/COMP2) output values can also generate break input signals for timers (TIM1/TIM8) on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of IO, see Section 37.3.17: Bidirectional...
Page 374 Peripherals interconnect matrix RM0432 10.3.15 From timers (TIM16/TIM17) to IRTIM Purpose General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output. The functionality is described in Section 43: Infrared interface (IRTIM). Active power mode Run, Sleep, Low-power run, Low-power sleep.
Page 375 RM0432 Direct memory access controller (DMA) Direct memory access controller (DMA) 11.1 Introduction The direct memory access (DMA) controller is a bus master and system peripheral. The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU. The DMA controller features a single AHB master architecture.
Page 376 Direct memory access controller (DMA) RM0432 11.3 DMA implementation 11.3.1 DMA1 and DMA2 DMA1 and DMA2 are implemented with the hardware configuration parameters shown in the table below. Table 48. DMA1 and DMA2 implementation Feature DMA1 DMA2 Number of channels 11.3.2 DMA request mapping The DMA controller is connected to DMA requests from the AHB/APB peripherals through...
Page 377 RM0432 Direct memory access controller (DMA) The DMA block diagram is shown in the figure below. Figure 31. DMA block diagram DMA1 Ch 1 Ch 2 AHB master interface Ch 7 dma1_req [1..7] Arbiter dma1_ack [1..7] Interrupt AHB slave interface interface dma1_it[1..7] DMA2...
Page 378 Direct memory access controller (DMA) RM0432 According to its configuration through the AHB slave interface, the DMA controller arbitrates between the DMA channels and their associated received requests. The DMA controller also schedules the DMA data transfers over the single AHB port master. The DMA controller generates an interrupt per channel to the interrupt controller.
Page 379 RM0432 Direct memory access controller (DMA) address register. The start address used for the first transfer is the base address of the peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx register. • post-decrementing of the programmed DMA_CNDTRx register This register contains the remaining number of data items to transfer (number of AHB ‘read followed by write’...
Page 380 Direct memory access controller (DMA) RM0432 Pointer incrementation The peripheral and memory pointers may be automatically incremented after each transfer, depending on the PINC and MINC bits of the DMA_CCRx register. If the incremented mode is enabled (PINC or MINC set to 1), the address of the next transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data size defined in PSIZE[1:0] or MSIZE[1:0].
Page 381 RM0432 Direct memory access controller (DMA) Channel state and disabling a channel A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0).
Page 382 Direct memory access controller (DMA) RM0432 automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. In order to stop a circular transfer, the software needs to stop the peripheral from generating DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
Page 383 RM0432 Direct memory access controller (DMA) Regardless of their usual naming, these ‘memory’ register, field and bit are used to define the destination peripheral in peripheral-to-peripheral mode. RM0432 Rev 6 383/2301...
Page 384 Direct memory access controller (DMA) RM0432 11.4.6 DMA data width, alignment and endianness When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data alignments as described in the table below. Table 50. Programmable data width and endian behavior (when PINC = MINC = 1) Source Destinat Destination...
Page 385 RM0432 Direct memory access controller (DMA) Addressing AHB peripherals not supporting byte/half-word write transfers When the DMA controller initiates an AHB byte or half-word write transfer, the data are duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]). When the AHB slave peripheral does not support byte or half-word write transfers and does not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two examples below:...
Page 386 Direct memory access controller (DMA) RM0432 11.5 DMA interrupts An interrupt can be generated on a half transfer, transfer complete or transfer error for each DMA channel x. Separate interrupt enable bits are available for flexibility. Table 51. DMA interrupt requests Interrupt Interrupt request Interrupt event...
Page 387 RM0432 Direct memory access controller (DMA) Bit 23 TEIF6: transfer error (TE) flag for channel 6 0: no TE event 1: a TE event occurred Bit 22 HTIF6: half transfer (HT) flag for channel 6 0: no HT event 1: a HT event occurred Bit 21 TCIF6: transfer complete (TC) flag for channel 6 0: no TC event 1: a TC event occurred...
Page 388 Direct memory access controller (DMA) RM0432 Bit 8 GIF3: global interrupt flag for channel 3 0: no TE, HT or TC event 1: a TE, HT or TC event occurred Bit 7 TEIF2: transfer error (TE) flag for channel 2 0: no TE event 1: a TE event occurred Bit 6 HTIF2: half transfer (HT) flag for channel 2...
Page 389 RM0432 Direct memory access controller (DMA) 11.6.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx, HTIFx, TCIFx, in the DMA_ISR register.
Page 390 Direct memory access controller (DMA) RM0432 Bit 8 CGIF3: global interrupt flag clear for channel 3 Bit 7 CTEIF2: transfer error flag clear for channel 2 Bit 6 CHTIF2: half transfer flag clear for channel 2 Bit 5 CTCIF2: transfer complete flag clear for channel 2 Bit 4 CGIF2: global interrupt flag clear for channel 2 Bit 3 CTEIF1: transfer error flag clear for channel 1 Bit 2 CHTIF1: half transfer flag clear for channel 1...
Page 391 RM0432 Direct memory access controller (DMA) Bits 11:10 MSIZE[1:0]: memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0.
Page 392 Direct memory access controller (DMA) RM0432 Bit 5 CIRC: circular mode 0: disabled 1: enabled Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). Bit 4 DIR: data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
Page 393 RM0432 Direct memory access controller (DMA) 11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res.
Page 394 Direct memory access controller (DMA) RM0432 Bits 31:0 PA[31:0]: peripheral address It contains the base address of the peripheral data register from/to which the data will be read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address.
Page 395 RM0432 Direct memory access controller (DMA) Table 52. DMA register map and reset values (continued) Offset Register DMA_IFCR 0x004 Reset value DMA_CCR1 0x008 Reset value DMA_CNDTR1 NDTR[15:0] 0x00C Reset value DMA_CPAR1 PA[31:0] 0x010 Reset value DMA_CMAR1 MA[31:0] 0x014 Reset value 0x018 Reserved Reserved.
Page 396 Direct memory access controller (DMA) RM0432 Table 52. DMA register map and reset values (continued) Offset Register DMA_CCR5 0x058 Reset value DMA_CNDTR5 NDTR[15:0] 0x05C Reset value DMA_CPAR5 PA[31:0] 0x060 Reset value DMA_CMAR5 MA[31:0] 0x064 Reset value 0x068 Reserved Reserved. DMA_CCR6 0x06C Reset value DMA_CNDTR6...
Page 397 RM0432 DMA request multiplexer (DMAMUX) DMA request multiplexer (DMAMUX) 12.1 Introduction A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending until it is served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA request signal is deasserted.
Page 398 DMA request multiplexer (DMAMUX) RM0432 12.2 DMAMUX main features • 14-channel programmable DMA request line multiplexer output • 4-channel DMA request generator • 26 trigger inputs to DMA request generator • 26 synchronization inputs • Per DMA request generator channel: –...
Page 399 RM0432 DMA request multiplexer (DMAMUX) Table 54. DMAMUX: assignment of multiplexer inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices) request Resource request Resource request Resource MUX input MUX input MUX input dmamux_req_gen0 TIM1_CH3 DFSDM1_FLT1 dmamux_req_gen1 TIM1_CH4 DFSDM1_FLT2 dmamux_req_gen2 TIM1_UP DFSDM1_FLT3 dmamux_req_gen3 TIM1_TRIG DCMI ADC1...
Page 400 DMA request multiplexer (DMAMUX) RM0432 Table 54. DMAMUX: assignment of multiplexer inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices) (continued) request Resource request Resource request Resource MUX input MUX input MUX input SAI1_B TIM15_TRIG Reserved SAI2_A TIM15_COM Reserved SAI2_B TIM16_CH1 Reserved OCTOSPI1 TIM16_UP Reserved...
Page 401 RM0432 DMA request multiplexer (DMAMUX) Table 55. DMAMUX: assignment of multiplexer inputs to resources (STM32L4P5xx and STM32L4Q5xx devices) (continued) request Resource request Resource request Resource MUX input MUX input MUX input I2C4_TX TIM3_TRIG Reserved USART1_RX TIM4_CH1 Reserved USART1_TX TIM4_CH2 Reserved USART2_RX TIM4_CH3 Reserved...
Page 402 DMA request multiplexer (DMAMUX) RM0432 Table 56. DMAMUX: assignment of trigger inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices) (continued) Trigger input Resource Trigger input Resource EXTI LINE11 Reserved EXTI LINE12 Reserved EXTI LINE13 Reserved EXTI LINE14 Reserved EXTI LINE15 Reserved Table 57.
Page 403 RM0432 DMA request multiplexer (DMAMUX) Table 58. DMAMUX: assignment of synchronization inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices) (continued) Sync. input Resource Sync. input Resource EXTI LINE7 DSI End of refresh EXTI LINE8 DMA2D End of Transfer EXTI LINE9 LTDC Line interrupt EXTI LINE10 Reserved EXTI LINE11...
Page 404 DMA request multiplexer (DMAMUX) RM0432 12.4 DMAMUX functional description 12.4.1 DMAMUX block diagram Figure 32 shows the DMAMUX block diagram. Figure 32. DMAMUX block diagram 32-bit AHB bus dmamux_hclk DMAMUX Request multiplexer AHB slave Channel m interface DMAMUX_CmCR Channel 1 Channel 0 DMA requests DMAMUX_C0CR...
Page 405 RM0432 DMA request multiplexer (DMAMUX) 12.4.2 DMAMUX signals Table 60 lists the DMAMUX signals. Table 60. DMAMUX signals Signal name Description dmamux_hclk DMAMUX AHB clock dmamux_req_inx DMAMUX DMA request line inputs from peripherals dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block) dmamux_req_genx DMAMUX request generator sub-block channels outputs DMAMUX request multiplexer sub-block inputs (from peripheral...
Page 406 DMA request multiplexer (DMAMUX) RM0432 Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected. It is not allowed to configure a same non-null DMAREQ_ID to two different channels of the DMAMUX request line multiplexer. On top of the DMA request selection, the synchronization mode and/or the event generation may be configured and enabled, if required.
Page 407 RM0432 DMA request multiplexer (DMAMUX) Figure 33. Synchronization mode of the DMAMUX request line multiplexer channel Selected DMA request line transferred to the output DMA requests served DMA request pending Selected dmamux_reqx Not pending dmamux_syncx dmamux_req_outx DMA request counter dmamux_evtx DMA request counter underrun Synchronization event DMA request counter auto-reload to NBREQ...
Page 408 DMA request multiplexer (DMAMUX) RM0432 Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request. Note: A synchronization event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles. Upon writing into DMAMUX_CxCR register, the synchronization events are masked during three AHB clock cycles.
Page 409 RM0432 DMA request multiplexer (DMAMUX) Note: The GNBREQ field value must be written by software only when the enable GE bit of the corresponding generator channel x is disabled. A trigger event (edge) is detected if the state following the edge remains stable for more than two AHB clock cycles.
Page 410 DMA request multiplexer (DMAMUX) RM0432 12.6 DMAMUX registers Refer to the table containing register boundary addresses for the DMAMUX base address. DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word. The address must be aligned with the data size. 12.6.1 DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR)
Page 411 RM0432 DMA request multiplexer (DMAMUX) Bit 7 Reserved, must be kept at reset value. Bits 6:0 DMAREQ_ID[6:0]: DMA request identification Selects the input DMA request. See the DMAMUX table about assignments of multiplexer inputs to resources. 12.6.2 DMAMUX request line multiplexer interrupt channel status register (DMAMUX_CSR) Address offset: 0x080 Reset value: 0x0000 0000...
Page 412 DMA request multiplexer (DMAMUX) RM0432 12.6.4 DMAMUX request generator channel x configuration register (DMAMUX_RGxCR) Address offset: 0x100 + 0x04 * x (x = 0 to 3) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] Res.
Page 413 RM0432 DMA request multiplexer (DMAMUX) 12.6.5 DMAMUX request generator interrupt status register (DMAMUX_RGSR) Address offset: 0x140 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 414 DMA request multiplexer (DMAMUX) RM0432 12.6.7 DMAMUX register map The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address. Table 62. DMAMUX register map and reset values Offset Register DMAREQ_ID[6:0]...
Page 415 RM0432 DMA request multiplexer (DMAMUX) Table 62. DMAMUX register map and reset values (continued) Offset Register 0x088 - Reserved 0x0FC DMAMUX_RG0CR GNBREQ[4:0] SIG_ID[4:0] 0x100 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAMUX_RG1CR GNBREQ[4:0] SIG_ID[4:0] 0x104...
Page 416 Chrom-ART Accelerator controller (DMA2D) RM0432 Chrom-ART Accelerator controller (DMA2D) 13.1 DMA2D introduction The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation. It can perform the following operations: • Filling a part or the whole of a destination image with a specific color •...
Page 417 RM0432 Chrom-ART Accelerator controller (DMA2D) • Area filling with a fixed color • Copy from an area to another • Copy with pixel format conversion between source and destination images • Copy from two sources with independent color format and blending •...
Page 418 Chrom-ART Accelerator controller (DMA2D) RM0432 Figure 35. DMA2D block diagram AHB MASTER FG PFC D mode 8-bit D Color mode D 32 Expander Expander FIFO OUT PFC BLENDER Color Color mode CLUT itf Converter FIFO 256x32-bit 32/24/16 Green Blue BG PFC D mode 8-bit D Color mode...
Page 419 RM0432 Chrom-ART Accelerator controller (DMA2D) They are programmed through a set of control registers: • DMA2D foreground memory address register (DMA2D_FGMAR) • DMA2D foreground offset register (DMA2D_FGOR) • DMA2D background memory address register (DMA2D_BGMAR) • DMA2D background offset register (DMA2D_BGBOR) •...
Page 420 Chrom-ART Accelerator controller (DMA2D) RM0432 The color format are coded as follows: • Alpha value field: transparency 0xFF value corresponds to an opaque pixel and 0x00 to a transparent one. • R field for Red • G field for Green •...
Page 421 RM0432 Chrom-ART Accelerator controller (DMA2D) The alpha channel can be: • kept as it is (no modification), • replaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR, • or replaced by the original alpha value multiplied by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255. Table 65.
Page 422 Chrom-ART Accelerator controller (DMA2D) RM0432 occurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in DMA2D_CR. • Manual loading The application has to program the CLUT manually through the DMA2D AHB slave port to which the local CLUT memory is mapped.The foreground CLUT is located at address offset 0x0400 and the background CLUT at address offset 0x0800.
Page 423 RM0432 Chrom-ART Accelerator controller (DMA2D) 13.3.7 DMA2D output PFC The output PFC performs the pixel format conversion from 32 bits to the output format defined in the CM[2:0] field of the DMA2D output pixel format converter configuration register (DMA2D_OPFCCR). The supported output formats are given in Table 68: Supported color mode in output Table 68.
Page 424 Chrom-ART Accelerator controller (DMA2D) RM0432 Table 69. Data order in memory (continued) Color Mode @ + 3 @ + 2 @ + 1 @ + 0 ARGB1555 [0]R [4:0]G [4:3] [2:0]B [4:0] [0]R [4:0]G [4:3] [2:0]B [4:0] ARGB4444 [3:0]R [3:0] [3:0]B [3:0] [3:0]R...
Page 425 RM0432 Chrom-ART Accelerator controller (DMA2D) 18/24-bit mode (RGB888) This mode needs data reordering. The Red and the Blue have to be swapped (setting the RBS bit) The MSB and the LSB bytes of an half-word as to be swapped (setting the SB bit) Figure 37.
Page 426 Chrom-ART Accelerator controller (DMA2D) RM0432 13.3.11 DMA2D transactions DMA2D transactions consist of a sequence of a given number of data transfers. The number of data and the width can be programmed by software. Each DMA2D data transfer is composed of up to 4 steps: Data loading from the memory location pointed by the DMA2D_FGMAR register and pixel format conversion as defined in DMA2D_FGCR.
Page 427 RM0432 Chrom-ART Accelerator controller (DMA2D) Memory-to-memory with PFC In this mode, the DMA2D performs a pixel format conversion of the source data and stores them in the destination memory location. The size of the areas to be transferred are defined by the DMA2D_NLR and DMA2D_FGOR registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the destination.
Page 428 Chrom-ART Accelerator controller (DMA2D) RM0432 The two pixel format converters have to be configured as described in the memory-to- memory mode. Their configurations can be different as each pixel format converter are independent and have their own CLUT memory. Once each pixel has been converted into 32 bits by their respective PFCs, they are blended according to the equation below: α...
Page 429 RM0432 Chrom-ART Accelerator controller (DMA2D) Once each pixel has been converted into 32 bits by their respective PFCs, they are blended together, and the resulting 32-bit pixel value is encoded by the output PFC according to the specified output format, and the data are written into the destination memory location pointed by DMA2D_OMAR.
Page 430 Chrom-ART Accelerator controller (DMA2D) RM0432 • Memory transfer: PL bits of DMA2D_NLR = 0 • Memory transfer: MODE bits of DMA2D_CR are invalid 13.3.13 DMA2D transfer control (start, suspend, abort and completion) Once the DMA2D is configured, the transfer can be launched by setting the START bit of the DMA2D_CR register.
Page 431 RM0432 Chrom-ART Accelerator controller (DMA2D) 13.4 DMA2D interrupts An interrupt can be generated on the following events: • Configuration error • CLUT transfer complete • CLUT access error • Transfer watermark reached • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 72.
Page 432 Chrom-ART Accelerator controller (DMA2D) RM0432 13.5 DMA2D registers 13.5.1 DMA2D control register (DMA2D_CR) Address offset: 0x0000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE[2:0] Res. Res. CEIE CTCIE CAEIE TWIE TCIE TEIE Res.
Page 433 RM0432 Chrom-ART Accelerator controller (DMA2D) Bit 9 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disable 1: TC interrupt enable Bit 8 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disable 1: TE interrupt enable Bit 7 Reserved, must be kept at reset value.
Page 434 Chrom-ART Accelerator controller (DMA2D) RM0432 13.5.2 DMA2D interrupt status register (DMA2D_ISR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 435 RM0432 Chrom-ART Accelerator controller (DMA2D) 13.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 436 Chrom-ART Accelerator controller (DMA2D) RM0432 13.5.5 DMA2D foreground offset register (DMA2D_FGOR) Address offset: 0x0010 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LO[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 LO[15:0]: Line offset The line offset used for the foreground image, expressed in pixel when the LOM bit is reset and in byte when the LOM bit is set.
Page 437 RM0432 Chrom-ART Accelerator controller (DMA2D) 13.5.7 DMA2D background offset register (DMA2D_BGOR) Address offset: 0x0018 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LO[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 LO[15:0]: Line offset The line offset used for the background image, expressed in pixel when the LOM bit is reset and in byte when the LOM bit is set.
Page 438 Chrom-ART Accelerator controller (DMA2D) RM0432 13.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) Address offset: 0x001C Reset value: 0x0000 0000 ALPHA[7:0] Res. Res. Res. Res. AM[1:0] CS[7:0] Res. Res. START CM[3:0] Bits 31:24 ALPHA[7:0]: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits.
Page 439 RM0432 Chrom-ART Accelerator controller (DMA2D) Bit 5 START: Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: – at the end of the transfer – when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR –...
Page 440 Chrom-ART Accelerator controller (DMA2D) RM0432 13.5.9 DMA2D foreground color register (DMA2D_FGCOLR) Address offset: 0x0020 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. RED[7:0] GREEN[7:0] BLUE[7:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 RED[7:0]: Red value These bits defines the red value for the A4 or A8 mode of the foreground image.
Page 441 RM0432 Chrom-ART Accelerator controller (DMA2D) 13.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) Address offset: 0x0024 Reset value: 0x0000 0000 ALPHA[7:0] Res. Res. Res. Res. AM[1:0] CS[7:0] Res. Res. START CM[3:0] Bits 31:24 ALPHA[7:0]: Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1:0].
Page 442 Chrom-ART Accelerator controller (DMA2D) RM0432 Bit 5 START: Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: – at the end of the transfer – when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR –...
Page 443 RM0432 Chrom-ART Accelerator controller (DMA2D) 13.5.11 DMA2D background color register (DMA2D_BGCOLR) Address offset: 0x0028 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. RED[7:0] GREEN[7:0] BLUE[7:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 RED[7:0]: Red value These bits define the red value for the A4 or A8 mode of the background.
Page 444 Chrom-ART Accelerator controller (DMA2D) RM0432 Bits 31:0 MA[31:0]: Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only.
Page 445 RM0432 Chrom-ART Accelerator controller (DMA2D) Bits 31:22 Reserved, must be kept at reset value. Bit 21 RBS: Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only. 0: Regular mode (RGB or ARGB) 1: Swap mode (BGR or ABGR) Bit 20 AI: Alpha Inverted...
Page 446 Chrom-ART Accelerator controller (DMA2D) RM0432 ARGB8888 or RGB888 color mode Bits 31:24 ALPHA[7:0]: Alpha channel value in ARGB8888 mode otherwise reserved These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 23:16 RED[7:0]: Red value in ARGB8888 or RGB888 mode otherwise reserved These bits define the red value of the output image.
Page 447 RM0432 Chrom-ART Accelerator controller (DMA2D) Bits 11:8 RED[3:0]: Red value in ARGB4444 mode These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. Bits 7:4 GREEN[3:0]: Green value in ARGB4444 mode These bits define the green value of the output image.
Page 448 Chrom-ART Accelerator controller (DMA2D) RM0432 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 LO[15:0]: Line offset The line offset used for the output expressed in pixel when the LOM bit is reset and in byte when the LOM bit is set. When expressed in pixels, only LO[13:0] is considered, LO[15:14] are ignored.
Page 449 RM0432 Chrom-ART Accelerator controller (DMA2D) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 LW[15:0]: Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled.
Page 450 Chrom-ART Accelerator controller (DMA2D) RM0432 Bits 31:24 ALPHA<y>[7:0]: Alpha <y> Alpha value for index <y> for the foreground. Bits 23:16 RED<y>[7:0]: Red <y> Red value for index <y> for the foreground. Bits 15:8 GREEN<y>[7:0]: Green <y> Green value for index <y> for the foreground. Bits 7:0 BLUE<y>[7:0]: Blue <y>...
Page 451 RM0432 Chrom-ART Accelerator controller (DMA2D) 13.5.23 DMA2D register map The following table summarizes the DMA2D registers. Refer to Section 2.2: Memory organization for the DMA2D register base address. Table 73. DMA2D register map and reset values Offset Register DMA2D_CR 0x0000 Reset value DMA2D_ISR 0x0004...
Page 452 Chrom-ART Accelerator controller (DMA2D) RM0432 Table 73. DMA2D register map and reset values (continued) Offset Register ALPHA[7:0] RED[7:0] GREEN[7:0] BLUE[7:0] RED[4:0] GREEN[5:0] BLUE[4:0] DMA2D_OCOLR 0x0038 RED[4:0] GREEN[4:0] BLUE[4:0] ALPHA[3:0] RED[3:0] GREEN[3:0] BLUE[3:0] Reset value DMA2D_OMAR MA[31:0] 0x003C Reset value DMA2D_OOR LO[15:0] 0x0040 Reset value...
Page 453 RM0432 Chrom-GRC™ (GFXMMU) Chrom-GRC™ (GFXMMU) 14.1 Introduction The graphic MMU is a graphical oriented memory management unit aimed to optimize memory usage according to the display shape. 14.2 Chrom-GRC™ main features • Fully programmable display shape to physically store only the visible pixel •...
Page 454 Chrom-GRC™ (GFXMMU) RM0432 14.3 Chrom-GRC™ functional and architectural description The graphic MMU is responsible of address resolution to convert the virtual buffer address into the physical buffer address. Figure 38. Chrom-GRC™ block diagram AHBSlaveAdd[23:0] Status registers Control registers Add[23:22] PhyAdd[22:0] pBuffer3AddMSB[31:23] pBuffer2AddMSB[31:23] pBuffer1AddMSB[31:23]...
Page 455 RM0432 Chrom-GRC™ (GFXMMU) Figure 39. Virtual buffer 16-byte block Out screen block 192/256 blocks (3072/4096 Byte) Line N first block on screen Line N+1 last block on screen Virtual buffer Configuration 192/256 x 16-byte blocks per line 1024 lines Continuous memory locations Physical buffer Line N first block on Line N last block...
Page 456 Chrom-GRC™ (GFXMMU) RM0432 Figure 40. Virtual buffer and physical buffer memory map Physical buffer Virtual buffer 0xFF:FFFF pBuffer3 0xDF:FFFF 0xYY:Y000 Physical buffer 3 offset Virtual buffer 3 (3/4 Mbyte) 0xXX00:0000 Physical buffer 3 base address 0xC0:0000 0xAF:FFFF pBuffer2 Virtual buffer 2 0xYY:Y000 Physical buffer 2 offset (3/4 Mbyte)
Page 457 RM0432 Chrom-GRC™ (GFXMMU) The MMU LUT is implemented as a 1024 x 35-bit RAM Figure 41. MMU block diagram Block[7:0] Line/block Add[21:4] [21:4] decoder Block0Offset[21:4] Overflow Line[9:0] LookUp LineEnable PhyAdd[22:4] FirstBlock[7:0] Block Add[23:4] Valid 1024 x 35-bit valid LastBlock[7:0] comp. Add[23:22] pBufferOffset[22:4] pBufferOffset...
Page 458 Chrom-GRC™ (GFXMMU) RM0432 A block is considered as valid i.e. physically mapped when • Line is enable • The block number is greater or equal to the first valid block • The block number is lower or equal to the last valid block When the block is valid, the physical address generated is considered as correct.
Page 459 RM0432 Chrom-GRC™ (GFXMMU) Example of calculation We are considering the following configuration for virtual buffer 0 • First visible block of line 0: block 7 • Number of visible block in line 0: 10 • First visible block of line 1: block 6 •...
Page 460 Chrom-GRC™ (GFXMMU) RM0432 14.4 Graphic MMU interrupts An interrupt can be produced on the following events: • Buffer 0 overflow • Buffer 1 overflow • Buffer 2 overflow • Buffer 3 overflow • AHB master error Separate interrupt enable bits are available for flexibility. Table 74.
Page 461 RM0432 Chrom-GRC™ (GFXMMU) 14.5 Graphic MMU registers 14.5.1 Graphic MMU configuration register (GFXMMU_CR) Address offset: 0x0000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 462 Chrom-GRC™ (GFXMMU) RM0432 14.5.2 Graphic MMU status register (GFXMMU_SR) Address offset: 0x0004 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 463 RM0432 Chrom-GRC™ (GFXMMU) Bit 2 CB2OF: Clear buffer 2 overflow flag Writing 1 clears the buffer 2 overflow flag in the GFXMMU_SR register. Bit 1 CB1OF: Clear buffer 1 overflow flag Writing 1 clears the buffer 1 overflow flag in the GFXMMU_SR register. Bit 0 CB0OF: Clear buffer 0 overflow flag Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register.
Page 464 Chrom-GRC™ (GFXMMU) RM0432 14.5.6 Graphic MMU buffer 1 configuration register (GFXMMU_B1CR) Address offset: 0x0024 Reset value: 0x0000 0000 PBBA[31:23] PBO[22:16] PBO[15:4] Res. Res. Res. Res. Bits 31:23 PBBA[31:23]: Physical buffer base address Base address MSB of the physical buffer. Bits 22:4 PBO[22:4]: Physical buffer offset Offset of the physical buffer.
Page 465 RM0432 Chrom-GRC™ (GFXMMU) 14.5.8 Graphic MMU buffer 3 configuration register (GFXMMU_B3CR) Address offset: 0x002C Reset value: 0x0000 0000 PBBA[31:23] PBO[22:16] PBO[15:4] Res. Res. Res. Res. Bits 31:23 PBBA[31:23]: Physical buffer base address Base address MSB of the physical buffer. Bits 22:4 PBO[22:4]: Physical buffer offset Offset of the physical buffer.
Page 466 Chrom-GRC™ (GFXMMU) RM0432 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LO[21:16] LO[15:4] Res. Res. Res. Res. Bits 31:22 Reserved, must be kept at reset value. Bits 21:4 LO[21:4]: Line offset Line offset of line number x (i.e. offset of block 0 of line x) Bits 3:0 Reserved, must be kept at reset value.
Page 467 RM0432 Chrom-GRC™ (GFXMMU) 14.5.11 Graphic MMU register map The following table summarizes the graphic MMU registers. Refer to the register boundary addresses table for the graphic MMU register base address. Table 75. Graphic MMU register map and reset values Offset Register GFXMMU_CR 0x0000...
Page 468 Nested vectored interrupt controller (NVIC) RM0432 Nested vectored interrupt controller (NVIC) 15.1 NVIC main features ® • 95 maskable interrupt channels (not including the sixteen Cortex -M4 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) •...
Page 469 RM0432 Nested vectored interrupt controller (NVIC) 15.3 Interrupt and exception vectors The gray rows in Table 76 describe the vectors without specific position. Table 76. STM32L4Rxxx and STM32L4Sxxx vector table Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004...
Page 470 Nested vectored interrupt controller (NVIC) RM0432 Table 76. STM32L4Rxxx and STM32L4Sxxx vector table (continued) Type of Acronym Description Address priority settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 0070 settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 0074 settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078 settable DMA1_CH5...
Page 471 RM0432 Nested vectored interrupt controller (NVIC) Table 76. STM32L4Rxxx and STM32L4Sxxx vector table (continued) Type of Acronym Description Address priority settable TIM8_UP TIM8 Update interrupt 0x0000 00F0 settable TIM8_TRG_COM TIM8 trigger and commutation interrupt 0x0000 00F4 settable TIM8_CC TIM8 capture compare interrupt 0x0000 00F8 settable Reserved...
Page 472 Nested vectored interrupt controller (NVIC) RM0432 Table 76. STM32L4Rxxx and STM32L4Sxxx vector table (continued) Type of Acronym Description Address priority settable OCTOSPI2 OCTOSPI2 global interrupt 0x0000 0170 settable TSC global interrupt 0x0000 0174 settable DSIHSOT DSI global interrupt 0x0000 0178 settable AES global interrupt 0x0000 017C...
Page 473 RM0432 Nested vectored interrupt controller (NVIC) Table 77. STM32L4P5xx and STM32Q5xx vector table (continued) Type of Acronym Description Address priority fixed HardFault All classes of fault 0x0000 000C settable MemManage Memory management 0x0000 0010 settable BusFault Pre-fetch fault, memory access fault 0x0000 0014 settable UsageFault...
Page 474 Nested vectored interrupt controller (NVIC) RM0432 Table 77. STM32L4P5xx and STM32Q5xx vector table (continued) Type of Acronym Description Address priority settable DMA1_CH7 DMA1 channel 7 interrupt 0x0000 0084 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000 0088 settable CAN1_TX CAN1_TX interrupts 0x0000 008C settable CAN1_RX0...
Page 475 RM0432 Nested vectored interrupt controller (NVIC) Table 77. STM32L4P5xx and STM32Q5xx vector table (continued) Type of Acronym Description Address priority settable TIM8_CC TIM8 capture compare interrupt 0x0000 00F8 settable SDMMC2 SDMMC2 global interrupt 0x0000 00FC settable FMC global interrupt 0x0000 0100 settable SDMMC1 SDMMC1 global interrupt...
Page 476 Nested vectored interrupt controller (NVIC) RM0432 Table 77. STM32L4P5xx and STM32Q5xx vector table (continued) Type of Acronym Description Address priority settable SAI2 SAI2 global interrupt 0x0000 016C settable OCTOSPI2 OCTOSPI2 global interrupt 0x0000 0170 settable TSC global interrupt 0x0000 0174 settable Reserved Reserved...
Page 477 RM0432 Extended interrupts and events controller (EXTI) Extended interrupts and events controller (EXTI) 16.1 Introduction The EXTI main features are as follows: • Generation of up to 39 event/interrupt requests – 26 configurable lines – 13 direct lines • Independent mask on each event/interrupt line •...
Page 478 MS33393V1 16.3.2 Wakeup event management The STM32L4+ Series devices are able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex -M4 System Control register.
Page 479 Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR). Set the required bit of the software interrupt register (EXTI_SWIER). 16.4 EXTI interrupt/event line mapping In the STM32L4+ Series, 39 interrupt/event lines are available. The GPIOs are connected to 16 configurable interrupt/event lines (see Figure 44).
Page 480 Extended interrupts and events controller (EXTI) RM0432 Figure 44. External interrupt/event GPIO mapping EXTI0[3:0] bits in the SYSCFG_EXTICR1 register EXTI0 EXTI1[3:0] bits in the SYSCFG_EXTICR1 register EXTI1 EXTI15[3:0] bits in the SYSCFG_EXTICR4 register PA15 PB15 PC15 PD15 EXTI15 PE15 PF15 PG15 PH15 MS46947V1...
Page 481 RM0432 Extended interrupts and events controller (EXTI) Table 78. EXTI lines connections (continued) EXTI line Line source Line type RTC tamper or timestamp or configurable CSS_LSE RTC wakeup timer configurable COMP1 output configurable COMP2 output configurable I2C1 wakeup direct I2C2 wakeup direct I2C3 wakeup direct...
Page 482 Extended interrupts and events controller (EXTI) RM0432 16.5 registers EXTI Refer to Section 1.2 on page 84 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 16.5.1 Interrupt mask register 1 (EXTI_IMR1) Address offset: 0x00 Reset value: 0xFF82 0000 IM31...
Page 483 RM0432 Extended interrupts and events controller (EXTI) Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 RT18 Res. RT16 RT15 RT14 RT13 RT12 RT11 RT10 Bits 31:23 Reserved, must be kept at reset value. Bits 22:18 RTx: Rising trigger event configuration bit of line x (x = 22 to 18) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line Bit 17 Reserved, must be kept at reset value.
Page 484 Extended interrupts and events controller (EXTI) RM0432 Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line.
Page 485 RM0432 Extended interrupts and events controller (EXTI) 16.5.6 Pending register 1 (EXTI_PR1) Address offset: 0x14 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 PIF18 Res. PIF16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 PIF15 PIF14 PIF13...
Page 486 Extended interrupts and events controller (EXTI) RM0432 16.5.8 Event mask register 2 (EXTI_EMR2) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 487 RM0432 Extended interrupts and events controller (EXTI) 16.5.10 Falling trigger selection register 2 (EXTI_FTSR2) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 488 Extended interrupts and events controller (EXTI) RM0432 16.5.12 Pending register 2 (EXTI_PR2) Address offset: 0x34 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 489 RM0432 Extended interrupts and events controller (EXTI) 16.5.13 EXTI register map Table 79 gives the EXTI register map and the reset values. Table 79. Extended interrupt/event controller register map and reset values Offset Register EXTI_IMR1 0x00 Reset value EXTI_EMR1 0x04 Reset value EXTI_RTSR1 0x08...
Page 490 Cyclic redundancy check calculation unit (CRC) RM0432 Cyclic redundancy check calculation unit (CRC) 17.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 491 RM0432 Cyclic redundancy check calculation unit (CRC) 17.3 CRC functional description 17.3.1 CRC block diagram Figure 45. CRC calculation unit block diagram 32-bit AHB bus 32-bit (read access) Data register (output) crc_hclk CRC computation 32-bit (write access) Data register (input) MS19882V2 17.3.2 CRC internal signals...
Page 492 Cyclic redundancy check calculation unit (CRC) RM0432 The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: •...
Page 493 RM0432 Cyclic redundancy check calculation unit (CRC) 17.4 CRC registers 17.4.1 CRC data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0] Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read.
Page 494 Cyclic redundancy check calculation unit (CRC) RM0432 17.4.3 CRC control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res.
Page 495 RM0432 Cyclic redundancy check calculation unit (CRC) Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value This register is used to write the CRC initial value. 17.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C1 1DB7 POL[31:16] POL[15:0] Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation.
Page 496 Flexible static memory controller (FSMC) RM0432 Flexible static memory controller (FSMC) 18.1 Introduction The flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND memory controller This memory controller is also named flexible memory controller (FMC). 18.2 FMC main features The FMC functional block makes the interface with: synchronous and asynchronous static...
Page 497 RM0432 Flexible static memory controller (FSMC) The Write FIFO can be disabled by setting the WFDIS bit in the FMC_BCR1 register. At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes. The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up.
Page 498 Flexible static memory controller (FSMC) RM0432 18.5 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 499 RM0432 Flexible static memory controller (FSMC) to any other value than 0, the FMC chip select (FMC_NEx) toggles between the consecutive accesses. This feature is required when interfacing with FRAM memory. • AHB transaction size is smaller than the memory size: The transfer may or not be consistent depending on the type of external device: –...
Page 500 Flexible static memory controller (FSMC) RM0432 Figure 47. FMC memory banks Supported memory type Address Bank 0x6000 0000 Bank 1 NOR/PSRAM/SRAM 4 x 64 Mbyte 0x6FFF FFFF 0x7000 0000 Not used 0x7FFF FFFF 0x8000 0000 Bank 3 NAND Flash memory 4 x 64 Mbyte 0x8FFF FFFF 0x9000 0000...
Page 501 RM0432 Flexible static memory controller (FSMC) 1. In case of a 16-bit external memory width, the FMC internally uses HADDR[25:1] to generate the address for external memory FMC_A[24:0]. Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0]. 18.6.2 NAND Flash memory address mapping The NAND bank is divided into memory areas as indicated in...
Page 502 Flexible static memory controller (FSMC) RM0432 18.7 NOR Flash/PSRAM controller The FMC generates the appropriate signal timings to drive the following types of memories: • Asynchronous SRAM, FRAM and ROM – 8 bits – 16 bits • PSRAM (CellularRAM™) – Asynchronous mode –...
Page 503 RM0432 Flexible static memory controller (FSMC) Table 87. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min. Max. Address Duration of the address AHB clock cycle Asynchronous setup setup phase (HCLK) Duration of the address hold Asynchronous, AHB clock cycle Address hold phase muxed I/Os...
Page 504 Flexible static memory controller (FSMC) RM0432 NOR Flash memory, 16-bit multiplexed I/Os Table 89. 16-bit multiplexed I/O NOR Flash memory FMC signal name Function Clock (for synchronous access) A[25:16] Address bus 16-bit multiplexed, bidirectional address/data bus (the 16-bit address AD[15:0] A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] Chip select, x = 1..4...
Page 505 RM0432 Flexible static memory controller (FSMC) Table 91. 16-Bit multiplexed I/O PSRAM (continued) FMC signal name I/O Function NE[x] Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM)) Output enable Write enable NL(= NADV) Address valid PSRAM input (memory signal name: NADV) NWAIT PSRAM wait input signal to the FMC NBL[1:0]...
Page 506 Flexible static memory controller (FSMC) RM0432 Table 92. NOR Flash/PSRAM: example of supported memories and transactions (continued) Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Use of byte lanes NBL[1:0] Asynchronous Asynchronous Asynchronous Split into 2 FMC accesses PSRAM Asynchronous Split into 2 FMC accesses...
Page 507 RM0432 Flexible static memory controller (FSMC) 18.7.4 NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash, PSRAM, SRAM, FRAM) • Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory • The FMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns) •...
Page 508 Flexible static memory controller (FSMC) RM0432 Figure 49. Mode 1 write access waveforms Memory transaction A[25:0] NBL[x:0] Data bus Data driven by controller NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1 HCLK HCLK cycles cycles MSv41665V1 The DATAHLD time at the end of the read and write transactions guarantee the address and data hold time after the NOE/NWE rising edge.
Page 509 RM0432 Flexible static memory controller (FSMC) Table 93. FMC_BCRx bitfields (mode 1) (continued) Bit number Bit name Value to set FACCEN Don’t care MWID As needed MTYP As needed, exclude 0x2 (NOR Flash memory) MUXE MBKEN Table 94. FMC_BTRx bitfields (mode 1) Bit number Bit name Value to set...
Page 510 Flexible static memory controller (FSMC) RM0432 Mode A - SRAM/FRAM/PSRAM (CRAM) OE toggling Figure 50. Mode A read access waveforms Memory transaction A[25:0] NBL[x:0] High Data bus Data driven by memory NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD HCLK HCLK cycles cycles MSv41681V1...
Page 511 RM0432 Flexible static memory controller (FSMC) Table 95. FMC_BCRx bitfields (mode A) Bit number Bit name Value to set 31:24 Reserved 0x000 23:22 NBLSET[1:0] As needed WFDIS As needed CCLKEN As needed CBURSTRW 0x0 (no effect in Asynchronous mode) 18:16 CPSIZE 0x0 (no effect in Asynchronous mode) ASYNCWAIT...
Page 512 Flexible static memory controller (FSMC) RM0432 Table 97. FMC_BWTRx bitfields (mode A) Bit number Bit name Value to set Duration of the data hold phase (DATAHLD+1 HCLK cycles for write 31:30 DATAHLD accesses). 29:28 ACCMOD 27:24 DATLAT Don’t care 23:20 CLKDIV Don’t care 19:16...
Page 513 RM0432 Flexible static memory controller (FSMC) Figure 53. Mode 2 write access waveforms Memory transaction A[25:0] NADV Data bus Data driven by controller ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1 HCLK cycles MSv41679V1 Figure 54. Mode B write access waveforms Memory transaction A[25:0] NADV...
Page 514 Flexible static memory controller (FSMC) RM0432 Table 98. FMC_BCRx bitfields (mode 2/B) Bit number Bit name Value to set 31:24 Reserved 0x000 23:22 NBLSET[1:0] Don’t care WFDIS As needed CCLKEN As needed CBURSTRW 0x0 (no effect in Asynchronous mode) 18:16 CPSIZE 0x0 (no effect in Asynchronous mode) ASYNCWAIT...
Page 515 RM0432 Flexible static memory controller (FSMC) Table 100. FMC_BWTRx bitfields (mode 2/B) Bit number Bit name Value to set Duration of the data hold phase (DATAHLD+1 HCLK cycles for write 31:30 DATAHLD accesses). 29:28 ACCMOD 0x1 if Extended mode is set 27:24 DATLAT Don’t care...
Page 516 Flexible static memory controller (FSMC) RM0432 Figure 56. Mode C write access waveforms Memory transaction A[25:0] NADV Data bus Data driven by controller ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1 HCLK cycles MSv41679V1 The differences compared with mode 1 are the toggling of NOE and the independent read and write timings.
Page 517 RM0432 Flexible static memory controller (FSMC) Table 101. FMC_BCRx bitfields (mode C) (continued) Bit number Bit name Value to set MWID As needed MTYP 0x02 (NOR Flash memory) MUXEN MBKEN Table 102. FMC_BTRx bitfields (mode C) Bit number Bit name Value to set Duration of the data hold phase (DATAHLD HCLK cycles for read 31:30...
Page 518 Flexible static memory controller (FSMC) RM0432 Mode D - asynchronous access with extended address Figure 57. Mode D read access waveforms Memory transaction A[25:0] NADV NBL[x:0] High Data bus Data driven by memory NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD HCLK HCLK...
Page 519 RM0432 Flexible static memory controller (FSMC) Figure 58. Mode D write access waveforms Memory transaction A[25:0] NADV NBL[x:0] Data bus Data driven by controller NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD +1 HCLK HCLK cycles HCLK cycles cycles MSv41684V1 The differences with mode 1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.
Page 520 Flexible static memory controller (FSMC) RM0432 Table 104. FMC_BCRx bitfields (mode D) (continued) Bit number Bit name Value to set Reserved FACCEN Set according to memory support MWID As needed MTYP As needed MUXEN MBKEN Table 105. FMC_BTRx bitfields (mode D) Bit number Bit name Value to set...
Page 521 RM0432 Flexible static memory controller (FSMC) Muxed mode - multiplexed asynchronous access to NOR Flash memory Figure 59. Muxed read access waveforms Memory transaction A[25:16] NADV NBL[x:0] High AD[15:0] Lower address Data driven by memory NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD HCLK...
Page 522 Flexible static memory controller (FSMC) RM0432 Figure 60. Muxed write access waveforms Memory transaction A[25:16] NADV NBL[x:0] AD[15:0] Lower address Data driven by controller NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD +1 HCLK HCLK cycles HCLK cycles cycles MSv41686V1 The difference with mode D is the drive of the lower address byte(s) on the data bus.
Page 523 RM0432 Flexible static memory controller (FSMC) Table 107. FMC_BCRx bitfields (Muxed mode) (continued) Bit number Bit name Value to set FACCEN MWID As needed MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM) MUXEN MBKEN Table 108. FMC_BTRx bitfields (Muxed mode) Bit number Bit name Value to set Duration of the data hold phase (DATAHLD HCLK cycles for read...
Page 524 Flexible static memory controller (FSMC) RM0432 The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ × HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: –...
Page 525 RM0432 Flexible static memory controller (FSMC) Figure 62. Asynchronous wait during a write access waveforms Memory transaction A[25:0] address phase data setup phase NWAIT don’t care don’t care 1HCLK D[15:0] data driven by FMC 3HCLK MSv40168V1 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. CellularRAM™...
Page 526 Flexible static memory controller (FSMC) RM0432 Data latency versus NOR memory latency The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register.
Page 527 RM0432 Flexible static memory controller (FSMC) In Burst mode, there are two timing configurations for the NOR Flash NWAIT signal: • The Flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset). • The Flash memory asserts the NWAIT signal during the wait state The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to the WAITCFG bit in the FMC_BCRx registers (x = 0..3).
Page 528 Flexible static memory controller (FSMC) RM0432 Figure 64. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) Memory transaction = burst of 4 half words HCLK A[25:16] addr[25:16] High NADV NWAIT (WAITCFG= (DATLAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data...
Page 529 RM0432 Flexible static memory controller (FSMC) Table 109. FMC_BCRx bitfields (Synchronous multiplexed read mode) (continued) Bit number Bit name Value to set Reserved WAITPOL To be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP...
Page 530 Flexible static memory controller (FSMC) RM0432 Figure 65. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) Memory transaction = burst of 2 half words HCLK A[25:16] addr[25:16] Hi-Z NADV NWAIT (WAITCFG = 0) (DATLAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data...
Page 531 RM0432 Flexible static memory controller (FSMC) Table 111. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued) Bit number Bit name Value to set To be set to 1 if the memory supports this feature, to be kept at 0 WAITEN otherwise. WREN WAITCFG Reserved...
Page 532 Flexible static memory controller (FSMC) RM0432 18.7.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control register for bank x (FMC_BCRx) (x = 1 to 4) Address offset: 8 * (x – 1), (x = 1 to 4) Reset value: Bank 1: 0x0000 30DB Reset value: Bank 2: 0x0000 30D2 Reset value: Bank 3: 0x0000 30D2 Reset value: Bank 4: 0x0000 30D2...
Page 533 RM0432 Flexible static memory controller (FSMC) Bit 20 CCLKEN: Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. 0: The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the FMC_BCRx register (default after reset).
Page 534 Flexible static memory controller (FSMC) RM0432 Bit 13 WAITEN: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode. 0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period).
Page 535 RM0432 Flexible static memory controller (FSMC) Bits 3:2 MTYP[1:0]: Memory type Defines the type of external memory attached to the corresponding memory bank. 00: SRAM/FRAM (default after reset for Bank 2...4) 01: PSRAM (CRAM) / FRAM 10: NOR Flash/OneNAND Flash (default after reset for Bank 1) 11: reserved Bit 1 MUXEN: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with...
Page 536 Flexible static memory controller (FSMC) RM0432 Bits 29:28 ACCMOD[1:0]: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: Access mode A 01: Access mode B 10: Access mode C 11: Access mode D...
Page 537 RM0432 Flexible static memory controller (FSMC) Bits 15:8 DATAST[7:0]: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 48 Figure 60), used in asynchronous accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 × HCLK clock cycles 0000 0010: DATAST phase duration = 2 ×...
Page 538 Flexible static memory controller (FSMC) RM0432 SRAM/NOR-Flash write timing registers x (FMC_BWTRx) Address offset: 0x104 + 8 * (x – 1), (x = 1 to 4) Reset value: 0x0FFF FFFF This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories.
Page 539 RM0432 Flexible static memory controller (FSMC) Bits 15:8 DATAST[7:0]: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 48 Figure 60), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 1 ×...
Page 540 Flexible static memory controller (FSMC) RM0432 Bits 31:20 Reserved, must be kept at reset value. Bit 19 CNTB4EN: Counter Bank 4 enable This bit enables the chip select counter for PSRAM/NOR Bank 4. 0: Counter disabled for Bank 4 1: Counter enabled for Bank 4 Bit 18 CNTB3EN: Counter Bank 3 enable This bit enables the chip select counter for PSRAM/NOR Bank 3.
Page 541 RM0432 Flexible static memory controller (FSMC) Table 113. Programmable NAND Flash access parameters (continued) Parameter Function Access mode Unit Min. Max. Number of clock cycles (HCLK) during which the address must be AHB clock cycle Memory hold held (as well as the data if a write Read/Write (HCLK) access is performed) after the...
Page 542 Flexible static memory controller (FSMC) RM0432 16-bit NAND Flash memory Table 115. 16-bit NAND Flash FMC signal name Function A[17] NAND Flash address latch enable (ALE) signal A[16] NAND Flash command latch enable (CLE) signal D[15:0] 16-bit multiplexed, bidirectional address/data bus Chip select NOE(= NRE) Output enable (memory signal name: read enable, NRE)
Page 543 RM0432 Flexible static memory controller (FSMC) 18.8.2 NAND Flash supported memories and transactions Table 116 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash controller are shown in gray. Table 116. Supported memories and transactions Memory Allowed/ Device...
Page 544 Flexible static memory controller (FSMC) RM0432 Figure 66. NAND Flash controller waveforms for common memory access HCLK A[25:0] NCEx High NREG, NIOW, NIOR MEMxSET MEMxHOLD MEMxWAIT + 1 NWE, MEMxHIZ + 1 write_data read_data Valid MS33733V3 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses. 2.
Page 545 RM0432 Flexible static memory controller (FSMC) to implement the prewait functionality needed by some NAND Flash memories (see details in Section 18.8.5: NAND Flash prewait functionality). The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank.
Page 546 Flexible static memory controller (FSMC) RM0432 When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the t timing. However any CPU read access to the NAND Flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of (MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.
Page 547 RM0432 Flexible static memory controller (FSMC) To perform an ECC computation: Enable the ECCEN bit in the FMC_PCR register. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. Read the ECC value available in the FMC_ECCR register and store it in a variable.
Page 548 Flexible static memory controller (FSMC) RM0432 Bits 12:9 TCLR[3:0]: CLE to RE delay Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space.
Page 549 RM0432 Flexible static memory controller (FSMC) FIFO status and interrupt register (FMC_SR) Address offset: 0x84 Reset value: 0x0000 0040 This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB. This is used to quickly write to the FIFO and free the AHB for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory.
Page 550 Flexible static memory controller (FSMC) RM0432 Bit 0 IRS: Interrupt rising edge status The flag is set by hardware and reset by software. 0: No interrupt rising edge occurred 1: Interrupt rising edge occurred Note: If this bit is written by software to 1 it is set. Common memory space timing register (FMC_PMEM) Address offset: Address: 0x88 Reset value: 0xFCFC FCFC...
Page 551 RM0432 Flexible static memory controller (FSMC) Bits 7:0 MEMSET[7:0]: Common memory x setup time Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space on socket x: 0000 0000: 1 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 552 Flexible static memory controller (FSMC) RM0432 Bits 7:0 ATTSET[7:0]: Attribute memory setup time Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on socket: 0000 0000: 1 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 553 RM0432 Flexible static memory controller (FSMC) 18.8.8 FMC register map Table 118. FMC register map and reset values Offset Register CPSIZE MWID MTYP FMC_BCR1 [2:0] [1:0] [1:0] 0x00 [1:0] Reset value CPSIZE MWID MTYP FMC_BCR2 [2:0] [1:0] [1:0] 0x08 [1:0] Reset value CPSIZE MWID...
Page 554 Flexible static memory controller (FSMC) RM0432 Table 118. FMC register map and reset values (continued) Offset Register BUSTURN FMC_BWTR1 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] [3:0] 0x104 Reset value BUSTURN FMC_BWTR2 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] [3:0] 0x10C Reset value BUSTURN FMC_BWTR3 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] [3:0] 0x114 Reset value...
Page 555 RM0432 Octo-SPI interface (OCTOSPI) Octo-SPI interface (OCTOSPI) 19.1 Introduction The OCTOSPI supports two frame formats used by most external serial memories such as serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAM™ and HyperFlash™ memories: • Indirect mode: all the operations are performed using the OCTOSPI registers. •...
Page 556 RM0432 19.3 OCTOSPI implementation The table below describes the OCTOSPI implementation on STM32L4+ Series devices. The full list of features is implemented in STM32L4P5xx and STM32L4Q5xx devices, while STM32L4Rxxx and STM32L4Sxxx devices support a reduced set of features Table 119. OCTOSPI implementation on STM32L4+ Series...
Page 557 RM0432 Octo-SPI interface (OCTOSPI) 19.4 OCTOSPI functional description 19.4.1 OCTOSPI block diagram Figure 68. OCTOSPI block diagram for octal communication Clock Registers/ management control Octo-SPI memory AHB/ OCTOSPI_CLK OCTOSPI_IO0 FIFO OCTOSPI_IO1 OCTOSPI_IO2 OCTOSPI_IO3 OCTOSPI_IO4 Shift OCTOSPI_IO5 register OCTOSPI_IO6 OCTOSPI_IO7 OCTOSPI_NCS OCTOSPI_DQS MSv43485V2 Figure 69.
Page 558 Octo-SPI interface (OCTOSPI) RM0432 Figure 70. OCTOSPI block diagram when dual-Flash is enabled Clock Registers/ management control AHB/ Quad-SPI memory 1 OCTOSPI_CLK OCTOSPI_IO0 Q0/SI FIFO OCTOSPI_IO1 Q1/SO OCTOSPI_IO2 Q2/WP OCTOSPI_IO3 Q3/HOLD OCTOSPI_nCS Shift register Quad-SPI memory 2 OCTOSPI_IO4 Q0/SI Q1/SO OCTOSPI_IO5 Q2/WP OCTOSPI_IO6...
Page 559 RM0432 Octo-SPI interface (OCTOSPI) The nCS falls before the start of each command and rises again after each command finishes. In Memory-mapped mode, both read and write operation are supported, as a consequence, some of the configuration registers are duplicated to specify write operations (read operations are configured using regular registers).
Page 560 Octo-SPI interface (OCTOSPI) RM0432 8 bits at a time (over IO0 to IO7 in Octal SPI mode). This can be configured using the ADMODE[2:0] field of the OCTOSPI_CCR register. The address can be sent in DTR mode (on each rising and falling edge of the clock) setting the ADDTR bit in OCTOSPI_CCR.
Page 561 RM0432 Octo-SPI interface (OCTOSPI) In order to assure enough “turn-around” time for changing the data signals from the output mode to the input mode, there must be at least one dummy cycle when using the Dual-SPI, the Quad-SPI or the Octal-SPI mode, to receive data from the external device. It is recommended to have at least five dummy cycles when using memories with DQS activated.
Page 562 Octo-SPI interface (OCTOSPI) RM0432 Figure 72. DTR read in Octal mode with DQS (Macronix mode) example IO[7:0] A[31:24] A[23:16] A[15:8] A[7:0] Word Word Dummy Address unit unit MSv43489V1 19.4.4 OCTOSPI Regular-command mode signal interface Single-SPI mode The legacy SPI mode allows just a single bit to be sent/received serially. In this mode, the data is sent to the external device over the SO signal (whose I/O are shared with IO0).
Page 563 RM0432 Octo-SPI interface (OCTOSPI) Quad-SPI mode In Quad-SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3 signals. The different phases can each be configured separately to use the Quad-SPI mode by setting to 011 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and OCTOSPI_WCCR).
Page 564 Octo-SPI interface (OCTOSPI) RM0432 Double-transfer rate (DTR) mode Each of the instruction/address/alternate/data phase can be configured to operate in Double-transfer rate (DTR) mode setting IDTR/ADDTR/ABDTR/DDTR bit in the OCTOSPI_CCR register. In Memory-mapped mode, the DTR mode for each phases of the write operations is specified in the OCTOSPI_WCCR register.
Page 565 RM0432 Octo-SPI interface (OCTOSPI) When reading the status registers of the devices in Dual-quad mode, twice as many bytes must be read compared to the same read in Regular mode: if each device gives eight valid bits after the instruction for fetching the status register, then the OCTOSPI must be configured with a data length of 2 bytes (16 bits), and the OCTOSPI receives one byte from each device.
Page 566 Octo-SPI interface (OCTOSPI) RM0432 Figure 75. Example of HyperBus read operation =Read Write Recovery = Initial Access High = 2x Latency Count Low = 1x Latency Count RWDS RWDS and Data Latency Count are edge aligned Dn+1 Dn+1 47:40 39:32 31:24 23:16 15:8...
Page 567 RM0432 Octo-SPI interface (OCTOSPI) During the read operation, the RWDS is used by the device, in two ways: • during the command/address phase, to request an additional latency • during the data phase, for data strobing Figure 76. HyperBus read operation with initial latency =Read Write Recovery = Initial Access High = 2x Latency Count...
Page 568 Octo-SPI interface (OCTOSPI) RM0432 Read and write operation with additional latency If the device needs an additional latency (during refresh period of a SDRAM for example), RWDS must be tied to one during one of the RWDS signals, during the command/address phase.
Page 569 RM0432 Octo-SPI interface (OCTOSPI) Write operation with no latency Some devices can also require a zero latency for the write operations. This zero write latency can be forced by setting the write zero latency (WZL) bit of OCTOSPI_HLCR). Figure 80. HyperBus write operation with no latency RWDS Memory drives RWDS but master ignores 23:16...
Page 570 Octo-SPI interface (OCTOSPI) RM0432 The CS boundary feature limits a transaction to a boundary of aligned addresses. The size of the address to be aligned with, is configured in the CS boundary CSBOUND[4:0] field of CSBOUND OCTOSPI_DCR3 and it is equal to 2 As an example, if CSBOUND(4:0] = 0x4, the boundary is set to 2 = 16 bytes.
Page 571 RM0432 Octo-SPI interface (OCTOSPI) 19.4.8 OCTOSPI Indirect mode In Indirect mode, the commands are started by writing to the OCTOSPI registers and the data is transferred by writing or reading the data register, in a similar way to other communication peripherals. When FMODE[1:0] = 0 in OCTOSPI_CR, the OCTOSPI is in Indirect-write mode: bytes are sent to the external device during the data phase.
Page 572 Octo-SPI interface (OCTOSPI) RM0432 Triggering the start of a transfer in HyperBus mode Depending on the OCTOSPI configuration, there are three different ways to trigger the start of a command in Indirect mode. In general, it is triggered as soon as the firmware gives the last information that is necessary for the command, and more specifically, a communication in Indirect mode starts at the moment when: •...
Page 573 RM0432 Octo-SPI interface (OCTOSPI) The access to the device begins in the same manner as in Indirect-read mode. The BUSY bit in OCTOSPI_SR goes high at this point and stays high even between the periodic accesses. The content of MASK[31:0] in OCTOSPI_PSMAR is used to mask the data from the external device in Automatic-polling mode: •...
Page 574 Octo-SPI interface (OCTOSPI) RM0432 after a period defined by TIMEOUT[15:0] in OCTOSPI_LPTR, when x cycles have elapsed without an access since the clock is inactive. BUSY goes high as soon as the first memory-mapped access occurs. Because of the prefetch operations, BUSY does not fall until there is an abort, or the peripheral is disabled. 19.4.11 OCTOSPI configuration introduction The OCTOSPI configuration is done in three steps:...
Page 575 RM0432 Octo-SPI interface (OCTOSPI) DEVSIZE[4:0] defines the size of external memory using the following formula: [DEVSIZE+1] Number of bytes in the device = 2 where DEVSIZE+1 is the number of address bits required to address the external device. The external device capacity can go up to 4 Gbytes (addressed using 32 bits) in Indirect mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes.
Page 576 Octo-SPI interface (OCTOSPI) RM0432 Status-flag polling mode configuration The Status-flag polling mode is enabled by setting FMODE[1:0] = 10. In this mode, the programmed frame is sent and the data is retrieved periodically. The maximum amount of data read in each frame is 4 bytes. If more data is requested in OCTOSPI_DLR, it is ignored and only 4 bytes are read.The periodicity is specified in OCTOSPI_PIR.
Page 577 RM0432 Octo-SPI interface (OCTOSPI) The data length register (OCTOSPI_DLR) has no meaning in Memory-mapped mode. When the OCTOSPI is used in Memory-mapped mode, the frames are constructed in the following way: Specify the frame timing in OCTOSPI_TCR for read operation. Specify the frame format in OCTOSPI_CCR for read operation.
Page 578 Octo-SPI interface (OCTOSPI) RM0432 19.4.15 OCTOSPI HyperBus mode configuration Indirect mode configuration When FMODE[1:0] = 00, the Indirect-write mode is selected and data can be sent to the external device. When FMODE[1:0] = 01, the Indirect-read mode is selected where data can be read from the external device.
Page 579 RM0432 Octo-SPI interface (OCTOSPI) Memory-mapped mode configuration In Memory-mapped mode, the external device is seen as an internal memory but with some latency during the accesses. Read and write operations are allowed to the external device in this mode. The Memory-mapped mode is entered by setting FMODE[1:0] = 11. The programmed instruction and frame is sent when an AHB master is accessing the memory mapped space.
Page 580 Octo-SPI interface (OCTOSPI) RM0432 Before setting ABORT, the software must ensure that all the current transactions are finished using the synchronization barriers. Note: Some devices may misbehave if a write operation to a status register is aborted. 19.4.18 OCTOSPI reconfiguration or deactivation Prior to any OCTOSPI reconfiguration, the software must ensure that all the transactions are completed: •...
Page 581 RM0432 Octo-SPI interface (OCTOSPI) must finish with a falling edge, the CLK is low when the nCS rises, and the CLK rises back up one half of a CLK cycle afterwards. Figure 84. nCS when CKMODE=1 in DDTR mode (T = CLK period) SCLK MSv44102V1 When the FIFO stays full during a read operation, or if the FIFO stays empty during a write...
Page 582 Octo-SPI interface (OCTOSPI) RM0432 Table 121. OCTOSPI interrupt requests Interrupt event Event flag Enable control bit Timeout TOIE Status match SMIE FIFO threshold FTIE Transfer complete TCIE Transfer error TEIE 19.6 OCTOSPI registers 19.6.1 OCTOSPI control register (OCTOSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 Res.
Page 583 RM0432 Octo-SPI interface (OCTOSPI) Bit 22 APMS: Automatic-poll mode stop This bit determines if the automatic polling is stopped after a match. 0: Automatic-polling mode is stopped only by abort or by disabling the OCTOSPI. 1: Automatic-polling mode stops as soon as there is a match. This bit can be modified only when BUSY=0 Bit 21 Reserved, must be kept at reset value.
Page 584 Octo-SPI interface (OCTOSPI) RM0432 Bit 7 FSEL: Flash select This bit selects the Flash memory to be addressed in Single/Dual/Quad mode in Single-Flash mode (when DQM = 0). 0: FLASH 1 selected (data exchanged over IO[3:0]) 1: FLASH 2 selected (data exchanged over IO[7:4]) This bit is ignored when DQM = 1 or when Octal mode is selected.
Page 585 RM0432 Octo-SPI interface (OCTOSPI) 19.6.2 OCTOSPI device configuration register 1 (OCTOSPI_DCR1) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. MTYP[2:0] Res. Res. Res. DEVSIZE[4:0] DLYBY CKMO Res. Res. CSHT[5:0] Res. Res. Res. Res. Res. FRCK Bits 31:27 Reserved, must be kept at reset value. Bits 26:24 MTYP[2:0]: Memory type This bit indicates the type of memory to be supported.
Page 586 Octo-SPI interface (OCTOSPI) RM0432 Bits 13:8 CSHT[5:0]: Chip-select high time CSHT + 1 defines the minimum number of CLK cycles where the chip-select (nCS) must remain high between commands issued to the external device. 0: nCS stays high for at least 1 cycle between external device commands. 1: nCS stays high for at least 2 cycles between external device commands.
Page 587 RM0432 Octo-SPI interface (OCTOSPI) Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating the CLK based on the kernel clock (value + 1). 0: F , kernel clock used directly as OCTOSPI CLK (prescaler bypassed). In this KERNEL case, if the DDR mode is used, it is mandatory to provide to the OCTOSPI a kernel clock that has 50% duty-cycle.
Page 588 Octo-SPI interface (OCTOSPI) RM0432 19.6.5 OCTOSPI device configuration register 4 (OCTOSPI_DCR4) Address offset: 0x0014 Reset value: 0x0000 0000 REFRESH[31:16] REFRESH[15:0] Bits 31:0 REFRESH[31:0]: Refresh rate This field enables the refresh rate feature. The nCS is released every REFRESH+1 clock cycles for writes, and REFRESH+4 clock cycles for reads.
Page 589 RM0432 Octo-SPI interface (OCTOSPI) Bit 3 SMF: Status match flag This bit is set in Automatic-polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR). It is cleared by writing 1 to CSMF. Bit 2 FTF: FIFO threshold flag In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any data left in the FIFO after the reads from the external device are complete.
Page 590 Octo-SPI interface (OCTOSPI) RM0432 19.6.8 OCTOSPI data length register (OCTOSPI_DLR) Address offset: 0x0040 Reset value: 0x0000 0000 DL[31:16] DL[15:0] Bits 31:0 DL[31: 0]: Data length Number of data to be retrieved (value+1) in Indirect and Status-polling modes. A value not greater than 3 (indicating 4 bytes) must be used for status polling-mode.
Page 591 RM0432 Octo-SPI interface (OCTOSPI) 19.6.10 OCTOSPI data register (OCTOSPI_DR) Address offset: 0x0050 Reset value: 0x0000 0000 DATA[31:16] DATA[15:0] Bits 31:0 DATA[31: 0]: Data Data to be sent/received to/from the external SPI device In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to the external device during the data phase.
Page 592 Octo-SPI interface (OCTOSPI) RM0432 19.6.12 OCTOSPI polling status match register (OCTOSPI_PSMAR) Address offset: 0x0088 Reset value: 0x0000 0000 MATCH[31:16] MATCH[15:0] Bits 31:0 MATCH[31: 0]: Status match Value to be compared with the masked status register to get a match This field can be written only when BUSY = 0. 19.6.13 OCTOSPI polling interval register (OCTOSPI_PIR) Address offset: 0x0090...
Page 593 RM0432 Octo-SPI interface (OCTOSPI) Bit 31 SIOO: Send instruction only once mode Sending the instruction only once (SIOO). This bit has no effect when IMODE = 00. 0: Send instruction on every transaction 1: Send instruction only for the first command This field can be written only when BUSY = 0.
Page 594 Octo-SPI interface (OCTOSPI) RM0432 Bits 15:14 Reserved, must be kept at reset value. Bits 13:12 ADSIZE[1:0]: Address size This field defines address size. 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bit 11 ADDTR: Address double transfer rate This bit sets the DTR mode for the address phase.
Page 595 RM0432 Octo-SPI interface (OCTOSPI) 19.6.15 OCTOSPI timing configuration register (OCTOSPI_TCR) Address offset: 0x0108 Reset value: 0x0000 0000 SSHIF Res. Res. DHQC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 596 Octo-SPI interface (OCTOSPI) RM0432 Bits 31:0 INSTRUCTION[31:0]: Instruction Instruction to be sent to the external SPI device This field can be written only when BUSY = 0. 19.6.17 OCTOSPI alternate bytes register (OCTOSPI_ABR) Address offset: 0x0120 Reset value: 0x0000 0000 ALTERNATE[31:16] ALTERNATE[15:0] Bits 31:0 ALTERNATE[31: 0]: Alternate bytes...
Page 597 RM0432 Octo-SPI interface (OCTOSPI) 19.6.19 OCTOSPI write communication configuration register (OCTOSPI_WCCR) Address offset: 0x0180 Reset value: 0x0000 0000 Res. Res. DQSE Res. DDTR DMODE[2:0] Res. Res. ABSIZE[1:0] ABDTR ABMODE[2:0] ADDT Res. Res. ADSIZE[1:0] ADMODE[2:0] Res. Res. ISIZE[1:0] IDTR IMODE[2:0] Bits 31:30 Reserved, must be kept at reset value. Bit 29 DQSE: DQS enable This bit enables the data strobe management.
Page 598 Octo-SPI interface (OCTOSPI) RM0432 Bits 18:16 ABMODE[2:0]: Alternate-byte mode This field defines the Alternate byte phase’s mode of operation. 000: No alternate bytes 001: Alternate bytes on a single line 010: Alternate bytes on two lines 011: Alternate bytes on four lines 100: Alternate bytes on eight lines 101-111: Reserved This field can be written only when BUSY = 0.
Page 599 RM0432 Octo-SPI interface (OCTOSPI) Bits 5:4 ISIZE[1:0]: Instruction size This bit defines instruction size: 00: 8-bit instruction 01: 16-bit instruction 10: 24-bit instruction 11: 32-bit instruction This field can be written only when BUSY = 0. Bit 3 IDTR: Instruction double transfer rate This bit sets the DTR mode for the instruction phase.
Page 600 Octo-SPI interface (OCTOSPI) RM0432 19.6.21 OCTOSPI write instruction register (OCTOSPI_WIR) Address offset: 0x0190 Reset value: 0x0000 0000 INSTRUCTION[31:16] INSTRUCTION[15:0] Bits 31:0 INSTRUCTION[31:0]: Instruction Instruction to be sent to the external SPI device This field can be written only when BUSY = 0. 19.6.22 OCTOSPI write alternate bytes register (OCTOSPI_WABR) Address offset: 0x01A0...
Page 601 RM0432 Octo-SPI interface (OCTOSPI) Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 TRWR[7:0]: Read write recovery time Device read write recovery time expressed in number of communication clock cycles Bits 15:8 TACC[7: 0]: Access time Device access time expressed in number of communication clock cycles Bits 7:2 Reserved, must be kept at reset value.
Page 602 Octo-SPI interface (OCTOSPI) RM0432 Table 122. OCTOSPI register map and reset values (continued) Offset Register OCTOSPI_FCR 0x0024 Reset value 0x0028 Reserved 0x003C OCTOSPI_DLR DL[31:0] 0x0040 Reset value 0x0044 Reserved OCTOSPI_AR ADDRESS[31:0] 0x0048 Reset value 0x004C Reserved OCTOSPI_DR DATA[31:0] 0x0050 Reset value 0x0054 Reserved 0x007C...
Page 603 RM0432 Octo-SPI interface (OCTOSPI) Table 122. OCTOSPI register map and reset values (continued) Offset Register OCTOSPI_IR INSTRUCTION[31:0] 0x0110 Reset value 0x0114 Reserved -0x011C OCTOSPI_ABR ALTERNATE[31:0] 0x0120 Reset value 0x0124 Reserved 0x012C OCTOSPI_LPTR TIMEOUT[15:0] 0x0130 Reset value 0x0134 Reserved 0x0200 OCTOSPI_WCCR 0x0180 Reset value OCTOSPI_WTCR...
Page 604 Fully programmable I/O matrix for pin assignment by function (data/control/clock) 20.3 OCTOSPIM implementation The table below describes the OCTOSPI implementation on STM32L4+ Series devices. The full list of features is implemented in STM32L4P5xx and STM32L4Q5xx devices, while STM32L4Rxxx and STM32L4Sxxx devices support a reduced set of features.
Page 605 RM0432 OCTOSPI I/O manager (OCTOSPIM) Figure 86. OCTOSPIM block diagram for SMT32L4P5xx and STM32L4Q5xx OCTOSPI I/O manager PnCR interface P1CR MUXEN OCTOSPIM_P1_CLK OCTOSPI1 OCTOSPIM_P1_NCLK sig. OCTOSPIM_P1_DQS OCTOSPI1 ACK1 OCTOSPIM_P1_NCS OCTOSPIM_P1_IO[7:0] REQ1 I/O Matrix Muxer OCTOSPIM_Pn_CLK OCTOSPIM_Pn_NCLK REQ2 OCTOSPIM_Pn_DQS OCTOSPI2 ACK2 OCTOSPIM_Pn_NCS OCTOSPIM_Pn_IO[7:0] OCTOSPI2...
Page 606 OCTOSPI I/O manager (OCTOSPIM) RM0432 20.4.2 OCTOSPIM matrix The OCTOSPI I/O manager matrix allows the user to set a fully programmable pre-mapping of functions: • Any OCTOSPIM_Pn_CLK / OCTOSPIM_Pn_NCLK pair can be mapped independently to OCTOSPI1_CLK/OCTOSPI1_NCLK or OCTOSPI2_CLK/OCTOSPI2_NCLK • Any OCTOSPIM_Pn_DQS can be mapped independently to OCTOSPI1_DQS or OCTOSPI2_DQS •...
Page 607 RM0432 OCTOSPI I/O manager (OCTOSPIM) 20.4.3 OCTOSPIM multiplexer When the Multiplexed mode is set, the two OCTOSPIs are multiplexed over the same bus. Both OCTOSPIs get the ownership of the bus in turn through a request/acknowledge protocol with REQ/ACK signals. The multiplexing is enabled by setting the MUXEN bit of the OCTOSPI I/O manager configuration register (OCTOSPIM_CR).
Page 608 OCTOSPI I/O manager (OCTOSPIM) RM0432 20.5 OCTOSPI I/O manager registers 20.5.1 OCTOSPI I/O manager control register (OCTOSPIM_CR) Address offset: 0x0000 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. REQ2ACK_TIME[7:0] Res. Res. Res. Res. Res. Res. Res. Res.
Page 609 RM0432 OCTOSPI I/O manager (OCTOSPIM) Bits 31:27 Reserved, must be kept at reset value. Bits 26:25 IOHSRC[1:0]: IO[7:4] Source for Port n This bits select the source of Port n IO[7:4]. 00: OCTOSPI1_IO[3:0] in non muxed mode / MUXED_IO[3:0] in muxed mode 01: OCTOSPI1_IO[7:4] in non muxed mode / MUXED_IO[7:4] in muxed mode 10: OCTOSPI2_IO[3:0] in non muxed mode / unused in muxed mode 11: OCTOSPI2_IO[7:4] in non muxed mode / unused in muxed mode...
Page 610 OCTOSPI I/O manager (OCTOSPIM) RM0432 Bits 3:2 Reserved, must be kept at reset value. Bit 1 CLKSRC: CLK/CLKn Source for Port n This bit selects the source of Port n CLK/CLKn. 0: OCTOSPI1_CLK/CLKn in non muxed mode / MUXED_CLK/CLKn in muxed mode 1: OCTOSPI2_CLK/CLKn in non muxed mode / unused port in muxed mode Bit 0 CLKEN: CLK/CLKn Enable for Port n This bit enables the Port n CLK/CLKn.
Page 611 RM0432 OCTOSPI I/O manager (OCTOSPIM) 20.5.3 OCTOSPIM register map The following table summarizes the OCTOSPI I/O manager registers. Refer to the register boundary addresses table for the OCTOSPI I/O manager register base address. Table 124. OCTOSPIM register map and reset values Offset Register name OCTOSPIM _CR REQ2ACK_TIME[7:0]...
Page 612 Analog-to-digital converters (ADC) RM0432 Analog-to-digital converters (ADC) 21.1 Introduction This section describes the implementation of up to 2 ADCs: • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master). Each ADC consists of a 12-bit successive approximation analog-to-digital converter. Each ADC has up to 19 multiplexed channels.
Page 613 RM0432 Analog-to-digital converters (ADC) 21.2 ADC main features • High-performance features – Up to 2 ADCs which can operate in dual mode: ADC1 is connected to 16 external channels + 3 internal channels ADC2 is connected to 16 external channels + 2 internal channels –...
Page 614 Analog-to-digital converters (ADC) RM0432 • Conversion modes – Each ADC can convert a single channel or can scan a sequence of channels – Single mode converts selected inputs once per trigger – Continuous mode converts selected inputs continuously – Discontinuous mode •...
Page 615 RM0432 Analog-to-digital converters (ADC) 21.4 ADC functional description 21.4.1 ADC block diagram Figure 88 shows the ADC block diagram and Table 127 gives the ADC pin description. Figure 88. ADC block diagram REF+ 1.62 to 3.6 V Cortex AREADY M4 with EOSMP ADC Interrupt JEOS...
Page 616 Analog-to-digital converters (ADC) RM0432 21.4.2 ADC pins and internal signals Table 126. ADC internal input/output signals Signal Internal signal name Description type Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers). EXT[15:0] Inputs These inputs are shared between the ADC master and the ADC slave.
Page 617 RM0432 Analog-to-digital converters (ADC) 21.4.3 ADC clocks Dual clock domain architecture The dual clock-domain architecture means that the ADC clock is independent from the AHB bus clock. The input clock is the same for all ADCs and can be selected between two different clock sources (see Figure 89: ADC clock scheme):...
Page 618 Analog-to-digital converters (ADC) RM0432 Figure 89. ADC clock scheme ADC1 and ADC2 (Reset and clock HCLK AHB interface controller) Bits CKMODE[1:0] of ADCx_CCR Analog ADC1 (master) /1 or /2 or /4 Others Analog ADC2 (slave) /1, 2, 4, 6, 8, 10, ADC12_CK 12, 16, 32, 64, 128, 256...
Page 619 RM0432 Analog-to-digital converters (ADC) 21.4.4 ADC1/2 connectivity ADC1 and ADC2 are tightly coupled and share some external channels as described in the below figures. Figure 90. ADC1 connectivity ADC1 Channel selection REFINT Fast channel REF− ADC12_INP1 Fast channel ADC12_INN1 ADC12_INP2 Fast channel ADC12_INN2 ADC12_INP3...
Page 620 Analog-to-digital converters (ADC) RM0432 Figure 91. ADC2 connectivity ADC2 ADC2 Channel selection REF− Fast channel REF− ADC12_INP1 Fast channel ADC12_INN1 ADC12_INP2 Fast channel ADC12_INN2 ADC12_INP3 Fast channel ADC12_INN3 ADC12_INP4 Fast channel ADC12_INN4 ADC12_INP5 Fast channel ADC12_INN5 ADC12_INP6 Slow channel ADC12_INN6 REF+ ADC12_INP7 Slow channel...
Page 621 RM0432 Analog-to-digital converters (ADC) 21.4.5 Slave AHB interface The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below: • Word (32-bit) accesses • Single cycle response • Response to all read/write accesses to the registers with zero wait states. The AHB slave interface does not support split/retry requests, and never generates AHB errors.
Page 622 Analog-to-digital converters (ADC) RM0432 21.4.7 Single-ended and differential input channels Channels can be configured to be either single-ended input or differential input by programming DIFSEL[i] bits in the ADC_DIFSEL register. This configuration must be written while the ADC is disabled (ADEN=0). Note that the DIFSEL[i] bits corresponding to single- ended channels are always programmed at 0.
Page 623 RM0432 Analog-to-digital converters (ADC) The internal analog calibration is lost each time the power of the ADC is removed (example, when the product enters in STANDBY or VBAT mode). In this case, to avoid spending time recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration.
Page 624 Analog-to-digital converters (ADC) RM0432 Figure 93. Updating the ADC calibration factor Converting channel Ready (not converting) Ready Converting channel ADC state (Single ended) (Single ended) Updating calibration Internal calibration factor[6:0] Start conversion (hardware or sofware) WRITE ADC_CALFACT CALFACT_S[6:0] by s/w by h/w MSv30529V2 Converting single-ended and differential analog inputs with a single ADC...
Page 625 RM0432 Analog-to-digital converters (ADC) 21.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) First of all, follow the procedure explained in Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN)). Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a stabilization time of t before it starts converting accurately, as shown in Figure...
Page 626 Analog-to-digital converters (ADC) RM0432 Figure 95. Enabling / disabling the ADC ADEN STAB ADRDY ADDIS Converting CH Startup state by S/W by H/W MSv30264V2 21.4.10 Constraints when writing the ADC control bits The software is allowed to write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the DIFSEL[i] control bits in the ADC_DIFSEL register and the control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN must be equal to 0).
Page 627 RM0432 Analog-to-digital converters (ADC) 21.4.11 Channel selection (SQRx, JSQRx) There are up to 19 multiplexed channels per ADC: • 5 fast analog inputs coming from GPIO pads (ADCx_INP/INN[1:5]) • Up to 11 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6:16]) •...
Page 628 Analog-to-digital converters (ADC) RM0432 21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2) Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level.
Page 629 RM0432 Analog-to-digital converters (ADC) 21.4.13 Single conversion mode (CONT=0) In Single conversion mode, the ADC performs once all the conversions of the channels. This mode is started with the CONT bit at 0 by either: • Setting the ADSTART bit in the ADC_CR register (for a regular channel) •...
Page 630 Analog-to-digital converters (ADC) RM0432 Note: To convert a single channel, program a sequence with a length of 1. It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. Injected channels cannot be converted continuously.
Page 631 RM0432 Analog-to-digital converters (ADC) 21.4.16 ADC timing The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: = [2.5 + 12.5 ] x T CONV...
Page 632 Analog-to-digital converters (ADC) RM0432 Note: In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (JADSTP must not be used). Figure 97. Stopping ongoing regular conversions Trigger Trigger Convert Sample Sample ADC state Ch(N-1) Ch(N-1) Ch(N) JADSTART Cleared by Cleared by ADSTART...
Page 633 RM0432 Analog-to-digital converters (ADC) 21.4.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN,JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity.
Page 634 Analog-to-digital converters (ADC) RM0432 Note: The regular trigger selection cannot be changed on-the-fly. The injected trigger selection can be anticipated and changed on-the-fly. Refer to Section 21.4.21: Queue of context for injected conversions on page 638 Each ADC master shares the same input triggers with its ADC slave as described in Figure Figure 99.
Page 635 RM0432 Analog-to-digital converters (ADC) Table 130. ADC1 - External triggers for regular channels (continued) Name Source Type EXTSEL[3:0] EXT10 TIM1_TRGO2 Internal signal from on-chip timers 1010 EXT11 TIM2_TRGO Internal signal from on-chip timers 1011 EXT12 TIM4_TRGO Internal signal from on-chip timers 1100 EXT13 TIM6_TRGO...
Page 636 Analog-to-digital converters (ADC) RM0432 reset and the injected channel sequence switches are launched (all the injected channels are converted once). Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence.
Page 637 RM0432 Analog-to-digital converters (ADC) Figure 100. Injected conversion latency ADCCLK Injection event Reset ADC max. latency ai16049b 1. The maximum latency value can be found in the electrical characteristics of the device datasheet. 21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) Regular group mode This mode is enabled by setting the DISCEN bit in the ADC_CFGR register.
Page 638 Analog-to-digital converters (ADC) RM0432 Note: The channel numbers referred to in the above example might not be available on all microcontrollers. When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than n conversions). When all subgroups are converted, the next trigger starts the conversion of the first subgroup.
Page 639 RM0432 Analog-to-digital converters (ADC) All the parameters of the context are defined into a single register ADC_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters: • The JSQR register can be written at any moment even when injected conversions are ongoing.
Page 640 Analog-to-digital converters (ADC) RM0432 Behavior when changing the trigger or sequence context Figure 101 Figure 102 show the behavior of the context Queue when changing the sequence or the triggers. Figure 101. Example of JSQR queue of context (sequence change) Write JSQR JSQR queue EMPTY...
Page 641 RM0432 Analog-to-digital converters (ADC) Queue of context: Behavior when a queue overflow occurs Figure 103 Figure 104 show the behavior of the context Queue if an overflow occurs before or during a conversion. Figure 103. Example of JSQR queue of context with overflow before conversion =>...
Page 642 Analog-to-digital converters (ADC) RM0432 It is recommended to manage the queue overflows as described below: • After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated). •...
Page 643 RM0432 Analog-to-digital converters (ADC) Figure 106. Example of JSQR queue of context with empty queue (case JQM=1) Queue becomes empty and triggers are ignored because JQM=1 Write JSQR JSQR EMPTY P1,P2 EMPTY EMPTY queue Ignored Ignored Trigger 1 EMPTY EMPTY (0x0000) EMPTY J context (returned by reading JQSR)
Page 644 Analog-to-digital converters (ADC) RM0432 Figure 108. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. Queue is flushed and maintains the last active context (P2 is lost) Write JSQR JSQR EMPTY...
Page 645 RM0432 Analog-to-digital converters (ADC) Figure 110. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) Queue is flushed and becomes empty (P2 is lost) Write JSQR EMPTY P1, P2 EMPTY EMPTY JSQR queue Reset by H/W by S/W JADSTP JADSTART Reset by S/W by H/W...
Page 646 Analog-to-digital converters (ADC) RM0432 Figure 112. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1) Queue is flushed and beomes empty (JSQR is read as 0x0000) JSQR queue P1, P2 EMPTY Reset ADDIS by S/W by H/W ADC J context EMPTY (0x0000) (returned by reading JSQR) ADC state...
Page 647 RM0432 Analog-to-digital converters (ADC) Table 132. T timings depending on resolution (ADC clock cycles) CONV (ns) at (ns) at CONV (with Sampling Time= (bits) = 30 MHz = 30 MHz (ADC clock cycles) 2.5 ADC clock cycles) 12.5 ADC clock cycles 416.67 ns 15 ADC clock cycles 500.0 ns...
Page 648 Analog-to-digital converters (ADC) RM0432 21.4.25 Timing diagrams example (single/continuous modes, hardware/software triggers) Figure 113. Single conversions of a sequence, software trigger ADSTART CH10 CH17 CH10 CH17 ADC state ADC_DR by s/w by h/w Indicative timings MS30549V1 1. EXTEN[1:0]=00, CONT=0 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 114.
Page 649 RM0432 Analog-to-digital converters (ADC) Figure 115. Single conversions of a sequence, hardware trigger ADSTART TRGX ADC state READY ADC_DR Indicative timings by s/w by h/w triggered ignored MS31013V2 1. TRGx (over-frequency) is selected as trigger source, EXTEN[1:0] = 01, CONT = 0 2.
Page 650 Analog-to-digital converters (ADC) RM0432 21.4.26 Data management Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN) Data and alignment At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADC_DR data register which is 16 bits wide. At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADC_JDRy data register which is 16 bits wide.
Page 651 RM0432 Analog-to-digital converters (ADC) Table 133. Offset computation versus data resolution (continued) Subtraction between raw converted data and offset Resolution Result Comments (bits converted RES[1:0]) Offset Data, left aligned DATA[11:4],00 Signed The user must configure OFFSET[3:0] 10: 8-bit OFFSET[11:0] 8-bit data to “0000”...
Page 652 Analog-to-digital converters (ADC) RM0432 Figure 118. Right alignment (offset enabled, signed value) 12-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT D11 10-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT 8-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT 6-bit data bit15 bit7...
Page 653 RM0432 Analog-to-digital converters (ADC) Figure 120. Left alignment (offset enabled, signed value) 12-bit data bit15 bit7 bit0 SEXT D11 10-bit data bit15 bit7 bit0 SEXT D9 8-bit data bit15 bit7 bit0 SEXT D7 6-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT MS31018V1 ADC overrun (OVR, OVRMOD)
Page 654 Analog-to-digital converters (ADC) RM0432 Figure 121. Example of overrun (OVR) ADSTART ADSTP TRGx ADC state STOP Overun ADC_DR read access ADC_DR (OVRMOD=0) ADC_DR (OVRMOD=1) by s/w by h/w triggered Indicative timings MS31019V1 Note: There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels.
Page 655 RM0432 Analog-to-digital converters (ADC) Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.
Page 656 Analog-to-digital converters (ADC) RM0432 The data format must be 16-bit signed: ADC_DR[15:12] = sign extended ADC_DR[11] = sign ADC_DR[11:0] = data To obtain 16-bit signed format in 12-bit ADC mode, the software needs to configure the OFFSETy[11:0] to 0x800 after having set OFFSETy_EN to 1. Only right aligned data format is available for the DFSDM interface (see Figure 118: Right alignment (offset enabled, signed...
Page 657 RM0432 Analog-to-digital converters (ADC) To stop a conversion in continuous auto-injection mode combined with autodelay mode (JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure: Wait until JEOS=1 (no more conversions are restarted) Clear JEOS, Set ADSTP=1 Read the regular data. If this procedure is not respected, a new regular sequence can restart if JEOS is cleared after ADSTP has been set.
Page 658 Analog-to-digital converters (ADC) RM0432 Figure 123. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) Not ignored Ignored (occurs during injected sequence) Regular trigger ADC state regular regular injected regular regular injected regular DLY (CH1) DLY (CH1) DLY (CH2) DLY (CH3) ADC_DR read access...
Page 659 RM0432 Analog-to-digital converters (ADC) Figure 124. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) Not ignored Ignored (occurs during injected sequence) Regular trigger DLY RDYCH2 RDY CH2 RDY CH5 RDY CH1 state regular regular regular regular injected injected regular DLY (CH1) DLY (CH1)
Page 660 Analog-to-digital converters (ADC) RM0432 Figure 125. AUTODLY=1, regular continuous conversions interrupted by injected conversions ADSTART state regular regular regular regular injected injected DLY (CH1) DLY (CH2) DLY (CH3) ADC_DR read access ADC_DR Ignored Injected trigger DLY (inj) JEOS ADC_JDR1 ADC_JDR2 by s/w by h/w Indicative timings...
Page 661 RM0432 Analog-to-digital converters (ADC) 21.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 127. Analog watchdog guarded area Analog voltage Higher threshold Guarded area Lower threshold...
Page 662 Analog-to-digital converters (ADC) RM0432 These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).
Page 663 RM0432 Analog-to-digital converters (ADC) ADCy_AWDx_OUT signal output generation Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADCy_AWDx_OUT signal as ETR.
Page 664 Analog-to-digital converters (ADC) RM0432 Figure 129. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7 STATE inside outside inside outside outside outside inside EOC FLAG not cleared by S/W AWDx FLAG ADCy_AWDx_OUT - Converting regular channels 1,2,3,4,5,6,7 - Regular channels 1,2,3,4,5,6,7 are all guarded MS31026V1 Figure 130.
Page 665 RM0432 Analog-to-digital converters (ADC) 21.4.30 Oversampler The oversampling unit performs data pre-processing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: –...
Page 666 Analog-to-digital converters (ADC) RM0432 Table 137. Maximum output results versus N and M (gray cells indicate truncation) No-shift 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Over shift shift shift shift shift shift shift shift sampling Raw data OVSS = OVSS = OVSS = OVSS =...
Page 667 RM0432 Analog-to-digital converters (ADC) Analog watchdog The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the following difference: – The RES[1:0] bits are ignored, comparison is always done on using the full 12-bit values HT[11:0] and LT[11:0] – the comparison is performed on the most significant 12-bit of the 16-bit oversampled results ADC_DR[15:4] Note:...
Page 668 Analog-to-digital converters (ADC) RM0432 Oversampling regular channels only The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion: • In continued mode, the accumulation restarts from the last valid data (prior to the conversion abort request due to the injected trigger).
Page 669 RM0432 Analog-to-digital converters (ADC) Oversampling regular and Injected channels It is possible to have both ROVSE and JOVSE bits set. In this case, the regular oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on Figure 136 below.
Page 670 Analog-to-digital converters (ADC) RM0432 Auto-injected mode It is possible to oversample auto-injected sequences and have all conversions results stored in registers to save a DMA resource. This mode is available only with both regular and injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations are not supported.
Page 671 RM0432 Analog-to-digital converters (ADC) 21.4.31 Dual ADC modes Dual ADC modes can be used in devices with two ADCs or more (see Figure 139). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in the ADCx_CCR register.
Page 672 Analog-to-digital converters (ADC) RM0432 Figure 139. Dual ADC block diagram Regular data register (16- bits) Injected data registers (4 Internal analog inputs x16-bits) ADCx_INN1 Regular ADCx_INP1 channels ADCx_INN2 Slave ADC ADCx_INP2 Injected channels Internal triggers Regular data register (16- bits) ADCx_INN16 Injected data registers (4 ADCx_INP16...
Page 673 RM0432 Analog-to-digital converters (ADC) Injected simultaneous mode This mode is selected by programming bits DUAL[4:0]=00101 This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL bits in the ADC_JSQR register).
Page 674 Analog-to-digital converters (ADC) RM0432 ongoing regular sequence and the associated delay phases are ignored. There is the same behavior for regular sequences occurring on the slave ADC. Regular simultaneous mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00110. This mode is performed on a regular group of channels.
Page 675 RM0432 Analog-to-digital converters (ADC) Figure 141. Regular simultaneous mode on 16 channels: dual ADC mode CH16 MASTER ADC SLAVE ADC CH16 CH14 CH13 CH12 Trigger End of regular sequence on MASTER and SLAVE ADC Sampling Conversion ai16054b If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a regular trigger event to occur (“n”...
Page 676 Analog-to-digital converters (ADC) RM0432 conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time). • The minimum possible DELAY is 1 to ensure that there is at least one cycle time between the opening of the analog switch of the master ADC sampling phase and the closing of the analog switch of the slave ADC sampling phase.
Page 677 RM0432 Analog-to-digital converters (ADC) Figure 143. Interleaved mode on 1 channel in single conversion mode: dual ADC mode 0.5 ADCCLK 0.5 ADCCLK cycle cycle MASTER ADC SLAVE ADC Trigger 4 ADCCLK End of conversion on 4 ADCCLK End of conversion on cycles master and slave ADC cycles...
Page 678 Analog-to-digital converters (ADC) RM0432 When the 1st trigger occurs, all injected master ADC channels in the group are converted. When the 2nd trigger occurs, all injected slave ADC channels in the group are converted. And so on. A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in the group have been converted.
Page 679 RM0432 Analog-to-digital converters (ADC) If the injected discontinuous mode is enabled for both master and slave ADCs: • When the 1st trigger occurs, the first injected channel of the master ADC is converted. • When the 2nd trigger occurs, the first injected channel of the slave ADC is converted. •...
Page 680 Analog-to-digital converters (ADC) RM0432 Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions.
Page 681 RM0432 Analog-to-digital converters (ADC) Figure 149. Interleaved single channel CH0 with injected sequence CH11, CH12 ADC1 (master) Conversions aborted ADC2 (slave) read read read read CH11 CH11 CH12 CH12 Legend: Injected trigger Resume (always restart with the master) Sampling Conversion MS34461V1 Figure 150.
Page 682 Analog-to-digital converters (ADC) RM0432 DMA requests in dual ADC mode In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for the slave) to transfer the data, like in single mode (refer to Figure 152: DMA Requests in regular simultaneous mode when MDMA=0b00).
Page 683 RM0432 Analog-to-digital converters (ADC) Figure 153. DMA requests in regular simultaneous mode when MDMA=0b10 Trigger Trigger Trigger Trigger ADC Master regular ADC Slave EOC ADC Slave regular ADC Slave EOC DMA request from ADC Master DMA request from ADC Slave Configuration where each sequence contains only one conversion MSv31033V2 Figure 154.
Page 684 Analog-to-digital converters (ADC) RM0432 Note: When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available. •...
Page 685 To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area.
Page 686 Analog-to-digital converters (ADC) RM0432 Where: • TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP. • TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP. • TS_DATA is the actual temperature sensor output value converted by ADC. Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points.
Page 687 RM0432 Analog-to-digital converters (ADC) 21.4.34 Monitoring the internal voltage reference It is possible to monitor the internal voltage reference (V ) to have a reference point for REFINT evaluating the ADC V voltage level. REF+ The internal voltage reference is internally connected to the input channel 0 of the ADC1 (ADC1_INP0).
Page 688 Analog-to-digital converters (ADC) RM0432 By replacing V by the formula provided above, the absolute voltage value is given by REF+ the following formula × VREFINT_CAL ADC_DATA × DDA_Charac -------------------------------------------------------------------------------------------------------------------- - CHANNELx × VREFINT_DATA FULL_SCALE For applications where V is known and ADC converted values are right-aligned, the absolute voltage value can be obtained by using the following formula: ------------------------------------ - ×...
Page 689 RM0432 Analog-to-digital converters (ADC) Table 139. ADC interrupts per each ADC (continued) Interrupt event Event flag Enable control bit End of sequence of conversions of an injected group JEOS JEOSIE Analog watchdog 1 status bit is set AWD1 AWD1IE Analog watchdog 2 status bit is set AWD2 AWD2IE Analog watchdog 3 status bit is set...
Page 690 Analog-to-digital converters (ADC) RM0432 21.6 ADC registers (for each ADC) Refer to Section 1.2 on page 84 for a list of abbreviations used in register descriptions. 21.6.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 691 RM0432 Analog-to-digital converters (ADC) Bit 5 JEOC: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register 0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
Page 692 Analog-to-digital converters (ADC) RM0432 21.6.2 ADC interrupt enable register (ADC_IER) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JQOVF EOSMP ADRDY Res. Res. Res. Res. Res.
Page 693 RM0432 Analog-to-digital converters (ADC) Bit 5 JEOCIE: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. 0: JEOC interrupt disabled. 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).
Page 694 Analog-to-digital converters (ADC) RM0432 21.6.3 ADC control register (ADC_CR) Address offset: 0x08 Reset value: 0x2000 0000 ADCA ADCA DEEP ADVREG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LDIF JADST JADST ADSTA Res. Res. Res. Res. Res.
Page 695 RM0432 Analog-to-digital converters (ADC) Bits 27:6 Reserved, must be kept at reset value. Bit 5 JADSTP: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured.
Page 696 Analog-to-digital converters (ADC) RM0432 Bit 2 ADSTART: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration).
Page 697 RM0432 Analog-to-digital converters (ADC) 21.6.4 ADC configuration register (ADC_CFGR) Address offset: 0x0C Reset value: 0x8000 0000 JAWD1 AWD1 AWD1S JDISC DISC JQDIS AWD1CH[4:0] JAUTO DISCNUM[2:0] EXTSE EXTSE EXTSE EXTSE DFSD Res. CONT EXTEN[1:0] ALIGN RES[1:0] MCFG Bit 31 JQDIS: Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : 0: Injected Queue enabled 1: Injected Queue disabled...
Page 698 Analog-to-digital converters (ADC) RM0432 Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels This bit is set and cleared by software 0: Analog watchdog 1 disabled on injected channels 1: Analog watchdog 1 enabled on injected channels Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing).
Page 699 RM0432 Analog-to-digital converters (ADC) Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. 000: 1 channel 001: 2 channels 111: 8 channels Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 700 Analog-to-digital converters (ADC) RM0432 Bit 12 OVRMOD: Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. 0: ADC_DR register is preserved with the old data when an overrun is detected. 1: ADC_DR register is overwritten with the last conversion result when an overrun is detected. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 701 RM0432 Analog-to-digital converters (ADC) Bit 2 DFSDMCFG: DFSDM mode configuration This bit is set and cleared by software to enable the DFSDM mode. It is effective only when DMAEN=0. 0: DFSDM mode disabled 1: DFSDM mode enabled Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0.
Page 702 Analog-to-digital converters (ADC) RM0432 Bit 10 ROVSM: Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. 0: Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence) 1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected...
Page 703 RM0432 Analog-to-digital converters (ADC) Bits 4:2 OVSR[2:0]: Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x 111: 256x Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).
Page 704 Analog-to-digital converters (ADC) RM0432 Bit 31 SMPPLUS: Addition of one clock cycle to the sampling time. 1: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers. 0: The sampling time remains set to 2.5 ADC clock cycles remains To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0.
Page 705 RM0432 Analog-to-digital converters (ADC) Bits 31:27 Reserved, must be kept at reset value. Bits 26:0 SMP[18:10][2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. 000: 2.5 ADC clock cycles 001: 6.5 ADC clock cycles 010: 12.5 ADC clock cycles...
Page 706 Analog-to-digital converters (ADC) RM0432 21.6.9 ADC watchdog threshold register 2 (ADC_TR2) Address offset: 0x24 Reset value: 0x00FF 0000 Res. Res. Res. Res. Res. Res. Res. Res. HT2[7:0] Res. Res. Res. Res. Res. Res. Res. Res. LT2[7:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2.
Page 707 RM0432 Analog-to-digital converters (ADC) Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 708 Analog-to-digital converters (ADC) RM0432 Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 1st in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 709 RM0432 Analog-to-digital converters (ADC) Bit 11 Reserved, must be kept at reset value. Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 6th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 710 Analog-to-digital converters (ADC) RM0432 Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 11th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 711 RM0432 Analog-to-digital converters (ADC) 21.6.15 ADC regular data register (ADC_DR) Address offset: 0x40 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 RDATA[15:0]: Regular data converted These bits are read-only.
Page 712 Analog-to-digital converters (ADC) RM0432 Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART=0 (which ensures that no injected conversion is ongoing).
Page 713 RM0432 Analog-to-digital converters (ADC) 21.6.17 ADC offset y register (ADC_OFRy) Address offset: 0x60 + 0x04 * (y -1), (y= 1 to 4) Reset value: 0x0000 0000 OFFSETy OFFSETy_CH[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 714 Analog-to-digital converters (ADC) RM0432 21.6.18 ADC injected channel y data register (ADC_JDRy) Address offset: 0x80 + 0x04 * (y - 1), (y = 1 to 4) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 715 RM0432 Analog-to-digital converters (ADC) 21.6.20 ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR) Address offset: 0xA4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3CH[18:16] AWD3CH[15:0] Bits 31:19 Reserved, must be kept at reset value. Bits 18:0 AWD3CH[18:0]: Analog watchdog 3 channel selection These bits are set and cleared by software.
Page 716 Analog-to-digital converters (ADC) RM0432 21.6.22 ADC Calibration Factors (ADC_CALFACT) Address offset: 0xB4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. CALFACT_D[6:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. CALFACT_S[6:0] Bits 31:23 Reserved, must be kept at reset value. Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode These bits are written by hardware or by software.
Page 717 RM0432 Analog-to-digital converters (ADC) JQOVF_ AWD3_ AWD2_ AWD1_ JEOS_ JEOC_ OVR_ EOS_ EOC_ EOSMP_ ADRDY_ Res. Res. Res. Res. Res. JQOVF_ AWD3_ AWD2_ AWD1_ JEOS_ JEOC_ OVR_ EOS_ EOC_ EOSMP_ ADRDY_ Res. Res. Res. Res. Res. Bits 31:27 Reserved, must be kept at reset value. Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
Page 718 Analog-to-digital converters (ADC) RM0432 Bit 5 JEOC_MST: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. Bit 4 OVR_MST: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. Bit 3 EOS_MST: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
Page 719 RM0432 Analog-to-digital converters (ADC) Bits 21:18 PRESC[3:0]: ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. 0000: input ADC clock not divided 0001: input ADC clock divided by 2 0010: input ADC clock divided by 4 0011: input ADC clock divided by 6...
Page 720 Analog-to-digital converters (ADC) RM0432 Bit 12 Reserved, must be kept at reset value. Bits 11:8 DELAY: Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 140 for the value of ADC resolution versus DELAY bits values.
Page 721 RM0432 Analog-to-digital converters (ADC) 21.7.3 ADC common regular data register for dual mode (ADC_CDR) Address offset: 0x0C (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 RDATA_SLV[15:0] RDATA_MST[15:0] Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC.
Page 722 Analog-to-digital converters (ADC) RM0432 Table 142. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) Offset Register ADC_ISR 0x00 Reset value ADC_IER 0x04 Reset value ADC_CR 0x08 Reset value DISCNUM AWD1CH[4:0] ADC_CFGR [2:0] [1:0] 0x0C...
Page 723 RM0432 Analog-to-digital converters (ADC) Table 142. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) Offset Register 0x44- Reserved Res. 0x48 JEXTSEL JSQ4[4:0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] JL[1:0] ADC_JSQR [3:0] 0x4C Reset value 0x50- Reserved Res.
Page 724 Analog-to-digital converters (ADC) RM0432 Table 142. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) Offset Register DIFSEL[18:0] ADC_DIFSEL 0xB0 Reset value CALFACT_D[6:0] CALFACT_S[6:0] ADC_CALFACT 0xB4 Reset value Table 143. ADC register map and reset values (master and slave ADC common registers) offset = 0x300 Offset Register...
Page 725 RM0432 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) 22.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 726 Digital-to-analog converter (DAC) RM0432 22.3 DAC implementation Table 144. DAC implementation DAC features DAC1 Dual channel Output buffer I/O connection DAC1_OUT1 on PA4, DAC1_OUT2 on PA5 Maximum sampling time 1MSPS Autonomous mode 726/2301 RM0432 Rev 6...
Page 727 RM0432 Digital-to-analog converter (DAC) 22.4 DAC functional description 22.4.1 DAC block diagram Figure 158. Dual-channel DAC block diagram VDDA VREF+ Offset calibration Sample & Hold Registers Control registers OTRIM1[5:0]bits TSAMPLE1 & logic Channel1 THOLD1 TSEL1[3:0] DMA_Request TREFRESH1 bits Buffer 1 TRIG DAC_DOR1 converter 1...
Page 728 Digital-to-analog converter (DAC) RM0432 The DAC includes: • Up to two output channels • The DAC_OUTx can be disconnected from the output pin and used as an ordinary GPIO • The DAC_OUTx can use an internal pin connection to on-chip peripherals such as comparator, operational amplifier and ADC (if available).
Page 729 RM0432 Digital-to-analog converter (DAC) mapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger. Figure 159. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710b •...
Page 730 Digital-to-analog converter (DAC) RM0432 22.4.4 DAC conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD). Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset).
Page 731 RM0432 Digital-to-analog converter (DAC) 22.4.6 DAC trigger selection If the TENx control bit is set, the conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[3:0] control bits determine which out of 16 pos- sible events triggers the conversion as shown in TSELx[3:0] bits of the DAC_CR register.
Page 732 Digital-to-analog converter (DAC) RM0432 22.4.7 DMA requests Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the value of the DAC_DHRx register is transferred into the DAC_DORx register when the transfer is complete, and a DMA request is generated.
Page 733 RM0432 Digital-to-analog converter (DAC) Figure 162. DAC LFSR register calculation algorithm ai14713c The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then transferred into the DAC_DORx register.
Page 734 Digital-to-analog converter (DAC) RM0432 22.4.9 DAC triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event.
Page 735 RM0432 Digital-to-analog converter (DAC) 22.4.10 DAC channel modes Each DAC channel can be configured in Normal mode or Sample and hold mode. The output buffer can be enabled to allow a high drive capability. Before enabling output buffer, the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded after reset) and can be adjusted by software during application operation.
Page 736 Digital-to-analog converter (DAC) RM0432 The timings for the three phases above are in units of LSI clock periods. As an example, to configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs assuming LSI ~32 KHz is selected: 12 cycles are required for sample phase: TSAMPLEx[9:0] = 11, 62 cycles are required for hold phase: THOLDx[9:0] = 62,...
Page 737 RM0432 Digital-to-analog converter (DAC) Figure 166. DAC Sample and hold mode phase diagram Sampling phase Hold phase Sampling phase Refresh phase MSv40462V2 Like in Normal mode, the Sample and hold mode has different configurations. To enable the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to: •...
Page 738 Digital-to-analog converter (DAC) RM0432 Table 148. Channel output modes summary (continued) MODE [2:0] Mode Buffer Output connections Connected to external pin Enabled Connected to external pin and to on chip peripherals (such as comparators) Sample and hold mode Connected to external pin and to on chip peripherals (such as comparators) Disabled Connected to on chip peripherals (such as comparators)
Page 739 RM0432 Digital-to-analog converter (DAC) If the DAC channel is active, write 0 to ENx bit in DAC_CR to disable the channel. Select a mode where the buffer is enabled, by writing to DAC_MCR register, MODEx[2:0] = 000b or 001b or 100b or 101b. Start the DAC channelx calibration, by setting the CENx bit in DAC_CR register to 1.
Page 740 Digital-to-analog converter (DAC) RM0432 When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB1 clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later). Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2.
Page 741 RM0432 Digital-to-analog converter (DAC) Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: Set the two DAC channel trigger enable bits TEN1 and TEN2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2 bitfields.
Page 742 Digital-to-analog converter (DAC) RM0432 Set the two DAC channel trigger enable bits TEN1 and TEN2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD).
Page 743 RM0432 Digital-to-analog converter (DAC) Set the two DAC channel trigger enable bits TEN1 and TEN2 Configure the same trigger source for both DAC channels by setting the same value in the TSEL1 and TSEL2 bitfields. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum amplitude value using the MAMPx[3:0] bits.
Page 744 Digital-to-analog converter (DAC) RM0432 Table 149. Effect of low-power modes on DAC (continued) Mode Description Standby The DAC peripheral is powered down and must be reinitialized after exiting Standby or Shutdown mode. Shutdown 22.6 DAC interrupts Table 150. DAC interrupts Interrupt Interrupt Enable...
Page 745 RM0432 Digital-to-analog converter (DAC) 22.7 DAC registers Refer to Section 1 on page 84 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 22.7.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU DMAE...
Page 746 Digital-to-analog converter (DAC) RM0432 Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 747 RM0432 Digital-to-analog converter (DAC) Bit 16 EN2: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. 0: DAC channel2 disabled 1: DAC channel2 enabled Note: These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC implementation.
Page 748 Digital-to-analog converter (DAC) RM0432 Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 0000: SWTRIG1 0001: dac_ch1_trig1 0010: dac_ch1_trig2 1111: dac_ch1_trig15 Refer to the trigger selection tables in Section 22.4.6: DAC trigger selection for details on trigger configuration and mapping.
Page 749 RM0432 Digital-to-analog converter (DAC) Bits 31:2 Reserved, must be kept at reset value. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. 0: No trigger 1: Trigger Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.
Page 750 Digital-to-analog converter (DAC) RM0432 Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1. Bits 3:0 Reserved, must be kept at reset value. 22.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
Page 751 RM0432 Digital-to-analog converter (DAC) 22.7.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) This register is available only on dual-channel DACs. Refer to Section 22.3: DAC implementation. Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res.
Page 752 Digital-to-analog converter (DAC) RM0432 22.7.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. DACC2DHR[11:0] Res. Res. Res. Res. DACC1DHR[11:0] Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
Page 753 RM0432 Digital-to-analog converter (DAC) 22.7.11 Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
Page 754 Digital-to-analog converter (DAC) RM0432 22.7.13 DAC channel2 data output register (DAC_DOR2) This register is available only on dual-channel DACs. Refer to Section 22.3: DAC implementation. Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 755 RM0432 Digital-to-analog converter (DAC) Bit 31 BWST2: DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete.
Page 756 Digital-to-analog converter (DAC) RM0432 22.7.15 DAC calibration control register (DAC_CCR) Address offset: 0x38 Reset value: 0x00XX 00XX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM2[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM1[4:0] Bits 31:21 Reserved, must be kept at reset value.
Page 757 RM0432 Digital-to-analog converter (DAC) Bits 18:16 MODE2[2:0]: DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored.
Page 758 Digital-to-analog converter (DAC) RM0432 22.7.17 DAC channel1 sample and hold sample time register (DAC_SHSR1) Address offset: 0x40 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 759 RM0432 Digital-to-analog converter (DAC) 22.7.19 DAC sample and hold time register (DAC_SHHR) Address offset: 0x48 Reset value: 0x0001 0001 Res. Res. Res. Res. Res. Res. THOLD2[9:0] Res. Res. Res. Res. Res. Res. THOLD1[9:0] Bits 31:26 Reserved, must be kept at reset value. Bits 25:16 THOLD2[9:0]: DAC channel2 hold time (only valid in Sample and hold mode).
Page 760 Digital-to-analog converter (DAC) RM0432 Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 TREFRESH2[7:0]: DAC channel2 refresh time (only valid in Sample and hold mode) Refresh time= (TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN2=0. These bits are available only on dual-channel DACs.
Page 761 RM0432 Digital-to-analog converter (DAC) 22.7.21 DAC register map Table 151 summarizes the DAC registers. Table 151. DAC register map and reset values Register Offset name DAC_CR 0x00 Reset value DAC_ SWTRGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0] DHR12L1...
Page 762 Digital-to-analog converter (DAC) RM0432 Table 151. DAC register map and reset values (continued) Register Offset name DAC_CCR OTRIM2[4:0] OTRIM1[4:0] 0x38 Reset value X X X X MODE2 MODE1 DAC_MCR [2:0] [2:0] 0x3C Reset value DAC_ TSAMPLE1[9:0] SHSR1 0x40 Reset value DAC_ TSAMPLE2[9:0] SHSR2...
Page 763 23.1 Introduction The STM32L4+ Series devices embed a voltage reference buffer which can be used as voltage reference for ADCs, DACs and also as voltage reference for external components through the VREF+ pin. When the VREF+ pin is double-bonded with VDDA pin in a package, the voltage reference buffer is not available and must be kept disabled (refer to datasheet for packages pinout description).
Page 764 Voltage reference buffer (VREFBUF) RM0432 23.3 VREFBUF registers 23.3.1 VREFBUF control and status register (VREFBUF_CSR) Address offset: 0x00 Reset value: 0x0000 0002 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 765 RM0432 Voltage reference buffer (VREFBUF) 23.3.2 VREFBUF calibration control register (VREFBUF_CCR) Address offset: 0x04 Reset value: 0x0000 00XX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 766 Digital camera interface (DCMI) RM0432 Digital camera interface (DCMI) 24.1 Introduction The digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
Page 767 RM0432 Digital camera interface (DCMI) 24.3.1 DCMI block diagram Figure 167 shows the DCMI block diagram. Figure 167. DCMI block diagram Control/Statusregister interface interface FIFO DCMI_PIXCLK Data Synchronizer Data extraction formatter DCMI_D[13:0], DCMI_HSYNC, DCMI_VSYNC ai5604c Figure 168. Top-level block diagram DCMI_D[13:0] DCMI_PIXCLK External...
Page 768 Digital camera interface (DCMI) RM0432 from the camera are stable and can be sampled. The maximum DCMI_PIXCLK period must be higher than 2.5 HCLK periods. 24.3.4 DCMI DMA interface The DMA interface is active when the CAPTURE bit of the DCMI_CR register is set. A DMA request is generated each time the camera interface receives a complete 32-bit data block in its register.
Page 769 RM0432 Digital camera interface (DCMI) Table 155. Positioning of captured data bytes in 32-bit words (8-bit width) Byte address 31:24 23:16 15:8 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 10-bit data When EDM[1:0] = 01 in DCMI_CR, the camera interface captures 10-bit data at its input DCMI_D[9:0] and stores them as the 10 least significant bits of a 16-bit word.
Page 770 Digital camera interface (DCMI) RM0432 Table 158. Positioning of captured data bytes in 32-bit words (14-bit width) Byte address 31:30 29:16 15:14 13:0 [13:0] [13:0] [13:0] [13:0] 24.3.6 DCMI synchronization The digital camera interface supports embedded or hardware (DCMI_HSYNC and DCMI_VSYNC) synchronization.
Page 771 RM0432 Digital camera interface (DCMI) capture is enabled (CAPTURE bit set in DCMI_CR), data transfer is synchronized with the deactivation of the DCMI_VSYNC signal (next start of frame). Transfer can then be continuous, with successive frames transferred by DMA to successive buffers or the same/circular buffer.
Page 772 Digital camera interface (DCMI) RM0432 detect a frame/line start or frame/line end. This means that there can be different codes for the frame/line start and frame/line end with the unmasked bit position remaining the same. Example FS = 0xA5 Unmask code for FS = 0x10 In this case the frame start code is embedded in the bit 4 of the frame start code.
Page 773 RM0432 Digital camera interface (DCMI) Figure 172. Frame capture waveforms in continuous grab mode DCMI_HSYNC DCMI_VSYNC Frame 1 captured Frame 2 captured ai15833b 1. Here, the active state of DCMI_HSYNC and DCMI_VSYNC is 1. 2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time. In continuous grab mode, the FCRC[1:0] bits in DCMI_CR can be configured to grab all pictures, every second picture or one out of four pictures to decrease the frame capture rate.
Page 774 Digital camera interface (DCMI) RM0432 If the DCMI_VSYNC signal goes active before the number of lines is specified in the DCMI_CWSIZE register, then the capture stops and an IT_FRAME interrupt is generated when enabled. Figure 174. Data capture waveforms DCMI_HSYNC DCMI_VSYNC HOFFCNT CAPCNT...
Page 775 RM0432 Digital camera interface (DCMI) 24.3.11 DCMI data format description Data formats Three types of data are supported: • 8/10/12/14-bit progressive video: either monochrome or raw Bayer format • YCbCr 4:2:2 progressive video • RGB565 progressive video. A pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits for green) takes two clock cycles to be transferred.
Page 776 Digital camera interface (DCMI) RM0432 The RGB planar format is compatible with standard OS frame buffer display formats. Only 16 BPP (bits per pixel): RGB565 (2 pixels per 32-bit word) is supported. The 24 BPP (palletized format) and gray-scale formats are not supported. Pixels are stored in a raster scan order, that is from top to bottom for pixel rows, and from left to right within a pixel row.
Page 777 RM0432 Digital camera interface (DCMI) Table 162. Data storage in YCbCr progressive video format - Y extraction mode Byte address 31:24 23:16 15:8 Y n + 3 Y n + 2 Y n + 1 Y n + 7 Y n + 6 Y n + 5 Y n + 4 Half resolution image extraction...
Page 778 Digital camera interface (DCMI) RM0432 24.5 DCMI registers Refer to Section 1.2 on page 84 for list of abbreviations used in register descriptions. All DCMI registers must be accessed as 32-bit words, otherwise a bus error occurs. 24.5.1 DCMI control register (DCMI_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 779 RM0432 Digital camera interface (DCMI) Bits 11:10 EDM[1:0]: Extended data mode 00: Interface captures 8-bit data on every pixel clock. 01: Interface captures 10-bit data on every pixel clock. 10: Interface captures 12-bit data on every pixel clock. 11: Interface captures 14-bit data on every pixel clock. Bits 9:8 FCRC[1:0]: Frame capture rate control These bits define the frequency of frame capture.
Page 780 Digital camera interface (DCMI) RM0432 Bit 0 CAPTURE: Capture enable 0: Capture disabled 1: Capture enabled The camera interface waits for the first start of frame, then a DMA request is generated to transfer the received data into the destination memory. In snapshot mode, the CAPTURE bit is automatically cleared at the end of the first frame received.
Page 781 RM0432 Digital camera interface (DCMI) 24.5.3 DCMI raw interrupt status register (DCMI_RIS) DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value.
Page 782 Digital camera interface (DCMI) RM0432 24.5.4 DCMI interrupt enable register (DCMI_IER) The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write. Address offset: 0x0C Reset value: 0x0000 0000 Res.
Page 783 RM0432 Digital camera interface (DCMI) 24.5.5 DCMI masked interrupt status register (DCMI_MIS) This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
Page 784 Digital camera interface (DCMI) RM0432 24.5.6 DCMI interrupt clear register (DCMI_ICR) The DCMI_ICR register is write-only. Setting a bit of this register clears the corresponding flag in the DCMI_RIS and DCMI_MIS registers. Writing 0 has no effect. Address offset: 0x14 Reset value: 0x0000 0000 Res.
Page 785 RM0432 Digital camera interface (DCMI) Bits 31:24 FEC[7:0]: Frame end delimiter code This byte specifies the code of the frame end delimiter. The code consists of 4 bytes in the form of 0xFF, 0x00, 0x00, FEC. If FEC is programmed to 0xFF, all the unused codes (0xFF0000XY) are interpreted as frame end delimiters.
Page 786 Digital camera interface (DCMI) RM0432 24.5.8 DCMI embedded synchronization unmask register (DCMI_ESUR) Address offset: 0x1C Reset value: 0x0000 0000 FEU[7:0] LEU[7:0] LSU[7:0] FSU[7:0] Bits 31:24 FEU[7:0]: Frame end delimiter unmask This byte specifies the mask to be applied to the code of the frame end delimiter. 0: The corresponding bit in the FEC byte in DCMI_ESCR is masked while comparing the frame end delimiter with the received data.
Page 787 RM0432 Digital camera interface (DCMI) Bits 31:29 Reserved, must be kept at reset value. Bits 28:16 VST[12:0]: Vertical start line count The image capture starts with this line number. Previous line data are ignored. 0x0000: line 1 0x0001: line 2 0x0002: line 3 ..
Page 788 Digital camera interface (DCMI) RM0432 BYTE3[7:0] BYTE2[7:0] BYTE1[7:0] BYTE0[7:0] Bits 31:24 BYTE3[7:0]: Data byte 3 Bits 23:16 BYTE2[7:0]: Data byte 2 Bits 15:8 BYTE1[7:0]: Data byte 1 Bits 7:0 BYTE0[7:0]: Data byte 0 788/2301 RM0432 Rev 6...
Page 789 RM0432 Digital camera interface (DCMI) 24.5.12 DCMI register map Table 164. DCMI register map and reset values Register Offset name DCMI_CR 0x00 Reset value DCMI_SR 0x04 Reset value DCMI_RIS 0x08 Reset value DCMI_IER 0x0C Reset value DCMI_MIS 0x10 Reset value DCMI_ICR 0x14 Reset value...
Page 790 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only The PSSI peripheral and the DCMI (digital camera interface) use the same circuitry. As a result, these two peripherals cannot be used at the same time: when using the PSSI, the DCMI registers cannot be accessed, and vice-versa.
Page 791 RM0432 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx 25.3.1 PSSI block diagram Figure 176. PSSI block diagram Control/Status interface Register FIFO/ PSSI_PDCK Data Data Synchronizer extraction formatter PSSI_D[15:0] PSSI_DE PSSI_RDY MSv48844V2 Figure 177. Top-level block diagram pssi_hclk PSSI_D[15:0] External interface PSSI_DE...
Page 792 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only Table 165. PSSI input/output pins PSSI signal DCMI signal it Signal type Description name is shared with PSSI_PDCK DCMI_PIXCK Input Parallel Data clock input Data output when transmitting, data input when PSSI_D[15:0] DCMI_D[13:0] Input/output...
Page 793 RM0432 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx Data register and DMA Data are transferred from/to the FIFO using the PSSI_DR data register: • In receive mode, data must be read from the FIFO by reading PSSI_DR. •...
Page 794 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only 16-bit data When EDM[1:0] in PSSI_CR are programmed to 11, the interface transfers 16 bits using the D[15:0] pins. In this case, two PSSI_PDCK cycles are required to transfer a 32-bit word. The least-significant half word (bits 15:0) correspond to the first half word transferred, and the most-significant half-word (bits 31:16) corresponds to the second half word transferred.
Page 795 RM0432 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx Figure 178. Data enable in receive mode waveform diagram (CKPOL=0) PSSI_PDCK PSSI_D[15:0] PSSI_DE MSv48846V2 If the PSSI_DE alternate output function is enabled (through DERDYCFG) in transmit mode (OUTEN=1), the PSSI drives PSSI_DE on the same PSSI_PDCK edge that the one used to drive the data (D[15:0]).
Page 796 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only If the PSSI_RDY alternate output function is enabled (through DERDYCFG) in receive mode (OUTEN=0), the PSSI drives PSSI_RDY one PSSI_PDCK half cycle after it samples the data (D[15:0]). If the FIFO has enough free space to receive more data, the PSSI drives the PSSI_RDY signal active.
Page 797 RM0432 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx Figure 181. Bidirectional PSSI_DE/PSSI_RDY waveform PSSI_PDCK PSSI_D[15:0] PSSI_DE PSSI_RDY MSv48849V2 Figure 182. Bidirectional PSSI_DE/PSSI_RDY connection diagram PSSI_D[15:0] PSSI_PDCK PSSI Master transmitter PSSI_DE_RDY MSv48850V2 25.4 PSSI interrupts The PSSI generates only one interrupt (IT_OVR). It is consequently equivalent to the global interrupt (pssi_it).
Page 798 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only 25.5 PSSI registers An 8-bit write or a 16-bit write operation to any PSSI register besides PSSI_DR will result in a bus error. 32-bit read and write operations are permitted. 25.5.1 PSSI control register (PSSI_CR) Address offset: 0x00...
Page 799 RM0432 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx Bit 14 ENABLE: PSSI enable 0: PSSI disabled 1: PSSI enabled The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself.
Page 800 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 801 RM0432 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx 25.5.4 PSSI interrupt enable register (PSSI_IER) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 802 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only Bits 31:2 Reserved, must be kept at reset value. Bit 1 OVR_MIS: Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1.
Page 803 RM0432 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx 25.5.7 PSSI data register (PSSI_DR) Address offset: 0x28 Reset value: 0x0000 0000 In receive mode (OUTEN=0), the DMA controller must read the received data from this register. Write operations to PSSI_DR result in an error response. When more bytes than the number of valid bytes are read in the FIFO, the invalid bytes return zeros.
Page 804 Parallel synchronous slave interface (PSSI) applied to STM32L4P5xx and STM32LQ5xx only 25.5.8 PSSI register map Table 170 summarizes the PSSI registers. Table 170. PSSI register map and reset values Offset Register PSSI_CR 0x00 Reset value 0 1 0 0 0 PSSI_SR 0x04 Reset value...
Page 805 RM0432 Comparator (COMP) Comparator (COMP) 26.1 Introduction The device embeds two ultra-low-power comparators COMP1, and COMP2 The comparators can be used for a variety of functions including: • Wakeup from low-power mode triggered by an analog signal, • Analog signal conditioning, •...
Page 806 Comparator (COMP) RM0432 26.3 COMP functional description 26.3.1 COMP block diagram The block diagram of the comparators is shown in Figure 183: Comparator block diagram. Figure 183. Comparator block diagram GPIO COMPx_INPSEL alternate function COMPx_POL COMPx_OUT COMPx_INP COMPx_INP I/Os COMPx COMPx_INM COMPx_VALUE COMPx_...
Page 807 RM0432 Comparator (COMP) Table 172. COMP1 input minus assignment (continued) COMP1_INM COMP1_INMSEL[2:0] ¾ V REFINT REFINT DAC Channel1 DAC Channel2 Table 173. COMP2 input plus assignment COMP2_INP COMP2_INPSEL Table 174. COMP2 input minus assignment COMP2_INM COMP2_INMSEL[2:0] ¼ V REFINT ½ V REFINT ¾...
Page 808 Comparator (COMP) RM0432 For this purpose, the comparator control and status registers can be write-protected (read- only). Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the whole register to become read-only, including the COMPx LOCK bit. The write protection can only be reset by a MCU reset.
Page 809 RM0432 Comparator (COMP) Figure 185. Comparator hysteresis INM - V hyst COMP_OUT MS19984V1 26.3.7 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes).It consists of a selection of a blanking window which is a timer output compare signal.
Page 810 Comparator (COMP) RM0432 26.3.8 COMP power and speed modes COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application. The bits PWRMODE[1:0] in COMPx_CSR registers can be programmed as follows: 00: High speed / full power 01 or 10: Medium speed / medium power 11: Low speed / ultra-low-power...
Page 811 RM0432 Comparator (COMP) Table 176. Interrupt control bits Enable control Exit from Sleep Exit from Stop Exit from Interrupt event Event flag mode modes Standby mode VALUE in COMP1 output through EXTI COMP1_CSR VALUE in COMP2 output through EXTI COMP2_CSR 26.6 COMP registers 26.6.1...
Page 812 Comparator (COMP) RM0432 Bit 22 BRGEN: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of the scaler. 0: Scaler resistor bridge disable (if BRGEN bit of COMP2_CSR register is also reset) 1: Scaler resistor bridge enable If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4 BGAP, 1/2 BGAP, 3/4 BGAP.
Page 813 RM0432 Comparator (COMP) Bits 3:2 PWRMODE[1:0]: Power Mode of the comparator 1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the Comparator 1. High speed 01 or 10: Medium speed Ultra low power Bit 1 Reserved, must be kept cleared.
Page 814 Comparator (COMP) RM0432 Bit 22 BRGEN: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of the scaler. 0: Scaler resistor bridge disable (if BRGEN bit of COMP1_CSR register is also reset) 1: Scaler resistor bridge enable If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4 BGAP, 1/2 BGAP, 3/4 BGAP.
Page 815 RM0432 Comparator (COMP) Bits 6:4 INMSEL: Comparator 2 input minus selection bits These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of comparator 2. 000 = 1/4 V REFINT 001 = 1/2 V REFINT...
Page 816 Comparator (COMP) RM0432 26.6.3 COMP register map The following table summarizes the comparator registers. Table 177. COMP register map and reset values Offset Register COMP1_CSR 0x00 Reset value COMP2_CSR 0x04 Reset value Refer to Section 2.2 on page 91 for the register boundary addresses. 816/2301 RM0432 Rev 6...
Page 817 RM0432 Operational amplifiers (OPAMP) Operational amplifiers (OPAMP) 27.1 Introduction The device embeds two operational amplifiers with two inputs and one output each. The three I/Os can be connected to the external pins, this enables any type of external interconnections. The operational amplifier can be configured internally as a follower or as an amplifier with a non-inverting gain ranging from 2 to 16.
Page 818 Operational amplifiers (OPAMP) RM0432 27.3.2 Initial configuration The default configuration of the operational amplifier is a functional mode where the three IOs are connected to external pins. In the default mode the operational amplifier uses the factory trimming values. See electrical characteristics section of the datasheet for factory trimming conditions, usually the temperature is 30 °C and the voltage is 3 V.
Page 819 RM0432 Operational amplifiers (OPAMP) 27.3.4 OPAMP modes The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers can be used in multiple configuration environments: • Standalone mode (external gain setting mode) • Follower configuration mode • PGA modes Note: The amplifier output pin is directly connected to the output pad to minimize the output impedance.
Page 820 Operational amplifiers (OPAMP) RM0432 Follower configuration mode The procedure to use the OPAMP in follower mode is presented hereafter. • configure OPAMODE bits as “internal follower” • configure VP_SEL bits as “GPIO connected to VINP”. • As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is copied to pin OPAMP_VOUT.
Page 821 RM0432 Operational amplifiers (OPAMP) Programmable Gain Amplifier mode The procedure to use the OPAMP to amplify the amplitude of an input signal is presented hereafter. • configure OPAMODE bits as “internal PGA enabled”, • configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”, •...
Page 822 Operational amplifiers (OPAMP) RM0432 Programmable Gain Amplifier mode with external filtering The procedure to use the OPAMP to amplify the amplitude of an input signal, with an external filtering, is presented hereafter. • configure OPAMODE bits as “internal PGA enabled”, •...
Page 823 RM0432 Operational amplifiers (OPAMP) The user is able to switch from ‘factory’ values to ‘user’ trimmed values using the USERTRIM bit in the OPAMP_CSR register. This bit is reset at startup and so the ‘factory’ value are applied by default to the OPAMP trimming registers. User is liable to change the trimming values in calibration or in functional mode.
Page 824 Operational amplifiers (OPAMP) RM0432 Calibration procedure Here are the steps to perform a full calibration of either one of the operational amplifiers: Select correct OPA_RANGE in OPAMP_CSR, then set the OPAEN bit in OPAMP_CSR to 1 to enable the operational amplifier. Set the USERTRIM bit in the OPAMP_CSR register to 1.
Page 825 RM0432 Operational amplifiers (OPAMP) Table 180. Effect of low-power modes on the OPAMP (continued) Mode Description Standby The OPAMP registers are powered down and must be re-initialized after exiting Standby or Shutdown mode. Shutdown 27.5 OPAMP registers 27.5.1 OPAMP1 control/status register (OPAMP1_CSR) Address offset: 0x00 Reset value: 0x0000 0000 OPA_...
Page 826 Operational amplifiers (OPAMP) RM0432 Bits 9:8 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 00: GPIO connected to VINM (valid also in PGA mode for filtering 01: Dedicated low leakage input, connected to VINM (valid also in PGA mode for filtering) 1x: Inverting input not externally connected.
Page 827 RM0432 Operational amplifiers (OPAMP) Reset value: 0x0000 XXXX (factory trimmed values) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIMLPOFFSETP[4:0] Res. Res. Res. TRIMLPOFFSETN[4:0] Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value.
Page 828 Operational amplifiers (OPAMP) RM0432 Bits 9:8 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 00:GPIO connected to VINM (valid also in PGA mode for filtering) 01: Dedicated low leakage input, (available only on BGA132) connected to VINM (valid also in PGA mode for filtering) 1x: Inverting input not externally connected.
Page 829 RM0432 Operational amplifiers (OPAMP) Reset value: 0x0000 XXXX (factory trimmed values) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIMLPOFFSETP[4:0] Res. Res. Res. TRIMLPOFFSETN[4:0] Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value.
Page 830 Digital filter for sigma delta modulators (DFSDM) RM0432 Digital filter for sigma delta modulators (DFSDM) 28.1 Introduction Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators. It is featuring up to 8 external digital serial interfaces (channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution.
Page 831 RM0432 Digital filter for sigma delta modulators (DFSDM) 28.2 DFSDM main features • Up to 8 multiplexed input digital serial channels: – configurable SPI interface to connect various Σ∆ modulators – configurable Manchester coded 1 wire interface support – clock output for Σ∆ modulator(s) •...
Page 832 Digital filter for sigma delta modulators (DFSDM) RM0432 28.3 DFSDM implementation This section describes the configuration implemented in DFSDMx. Table 182. STM32L4Rxxx and STM32L4Sxxx DFSDM1 implementation DFSDM features DFSDM1 Number of channels Number of filters Input from internal ADC Supported trigger sources Pulses skipper ID registers support 1.
Page 833 RM0432 Digital filter for sigma delta modulators (DFSDM) 28.4 DFSDM functional description 28.4.1 DFSDM block diagram Figure 191. Single DFSDM block diagram APB bus ADC 0 ADC 7 Sample 1 Sample 0 Parallel input data register 0 Sample 1 Sample 0 Parallel input data register 7 EXTRG[1:0]...
Page 834 Digital filter for sigma delta modulators (DFSDM) RM0432 28.4.2 DFSDM pins and internal signals Table 184. DFSDM external pins Name Signal Type Remarks Power supply Digital power supply. Power supply Digital ground power supply. CKIN[7:0] Clock input Clock signal provided from external Σ∆ modulator. FT input. DATIN[7:0] Data input Data signal provided from external Σ∆...
Page 835 RM0432 Digital filter for sigma delta modulators (DFSDM) Table 186. DFSDM triggers connection (continued) Trigger name Trigger source dfsdm_jtrg24 EXTI11 dfsdm_jtrg25 EXTI15 dfsdm_jtrg26 LTIMER1 dfsdm_jtrg[31:27] Reserved Table 187. DFSDM break connection Break name Break destination dfsdm_break[0] TIM1/TIM15 break dfsdm_break[1] TIM1 break2 / TIM16 break dfsdm_break[2] TIM8/TIM17 break dfsdm_break[3]...
Page 836 Digital filter for sigma delta modulators (DFSDM) RM0432 DFSDM clocks The internal DFSDM clock f , which is used to drive the channel transceivers, DFSDMCLK digital processing blocks (digital filter, integrator) and next additional blocks (analog watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC block and is derived from the system clock SYSCLK or peripheral clock PCLK2 (see Section 6.4.32: Peripherals independent clock configuration register (RCC_CCIPR2)).
Page 837 RM0432 Digital filter for sigma delta modulators (DFSDM) Configuration of serial channels for PDM microphone input: • PDM microphone signals (data, clock) will be connected to DFSDM input serial channel y (DATINy, CKOUT) pins. • Channel y will be configured: CHINSEL = 0 (input from given channel pins: DATINy, CKINy).
Page 838 Digital filter for sigma delta modulators (DFSDM) RM0432 Output clock generation A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs. The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV bits in DFSDM_CH0CFGR1 register).
Page 839 RM0432 Digital filter for sigma delta modulators (DFSDM) decoding. There are two possible settings of Manchester codings (see SITP[1:0] bits in DFSDM_CHyCFGR1 register): • signal rising edge = log 0; signal falling edge = log 1 • signal rising edge = log 1; signal falling edge = log 0 The recovered clock signal frequency for Manchester coding must be in the range 0 - 10 MHz and less than f DFSDMCLK...
Page 840 Digital filter for sigma delta modulators (DFSDM) RM0432 Figure 193. Channel transceiver timing diagrams (SPICKSEL=0) SITP = 00 SITP = 01 SPICKSEL=3 SPICKSEL=2 SPICKSEL=1 SITP = 0 SITP = 1 SITP = 2 SITP = 3 recovered clock recovered data MS30766V3 840/2301 RM0432 Rev 6...
Page 841 RM0432 Digital filter for sigma delta modulators (DFSDM) Clock absence detection Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1 register.
Page 842 Digital filter for sigma delta modulators (DFSDM) RM0432 The detection of a clock absence in Manchester coding (after a first successful synchronization) is based on changes comparison of coded serial data input signal with output clock generation (CKOUT signal). There must be a voltage level change on DATINy pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in DFSDM_CH0CFGR1 register).
Page 843 RM0432 Digital filter for sigma delta modulators (DFSDM) Manchester/SPI code synchronization The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence detailed hereafter:...
Page 844 Digital filter for sigma delta modulators (DFSDM) RM0432 Figure 196. First conversion for Manchester coding (Manchester synchronization) SITP = 2 SITP = 3 recovered clock data from modulator CHEN real start of first conversion first conversion start trigger first data bit toggle - end of Manchester synchronization recovered data CKABF[y] clearing of CKABF[y] flag by software polling...
Page 845 RM0432 Digital filter for sigma delta modulators (DFSDM) Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not interrupt the conversion for correct conversion duration result. Conversion times: injected conversion or regular conversion with FAST = 0 (or first conversion if FAST=1):...
Page 846 Digital filter for sigma delta modulators (DFSDM) RM0432 the final output sample (and next samples) from filter will be calculated from later input data. This final sample then looks a bit in forward - because it is calculated from newer input samples than the “non-skipped”...
Page 847 RM0432 Digital filter for sigma delta modulators (DFSDM) Each channel contains a 32-bit data input register DFSDM_CHyDATINR in which it can be written a 16-bit data. Data are in 16-bit signed format. Those data can be used as input to the digital filter which is accepting 16-bit parallel data.
Page 848 Digital filter for sigma delta modulators (DFSDM) RM0432 filter must perform two input samplings from channel y to empty DFSDM_CHyDATINR register. This mode is used together with 32-bit CPU/DMA access to DFSDM_CHyDATINR register to load two samples per write operation. Dual mode (DATPACK[1:0]=2): Two samples are written into DFSDM_CHyDATINR register.
Page 849 RM0432 Digital filter for sigma delta modulators (DFSDM) Injected conversions can operate in scan mode (JSCAN=1) or single mode (JSCAN=0). In scan mode, each of the selected channels is converted, one after another. The lowest channel (channel 0, if selected) is converted first, followed immediately by the next higher channel until all the channels selected by JCHG[7:0] have been converted.
Page 850 Digital filter for sigma delta modulators (DFSDM) RM0432 Figure 198. Example: Sinc filter response Normalized frequency (f DATA MS30770V1 Table 188. Filter maximum output resolution (peak data values from filter output) for some FOSR values FOSR Sinc Sinc FastSinc Sinc Sinc Sinc +/- x...
Page 851 RM0432 Digital filter for sigma delta modulators (DFSDM) Table 189. Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc filter type (largest data) IOSR Sinc Sinc FastSinc Sinc Sinc Sinc +/- FOSR.
Page 852 Digital filter for sigma delta modulators (DFSDM) RM0432 There are 2 options for comparing the threshold registers with the data values • Option1: in this case, the input data are taken from final output data register (AWFSEL=0). This option is characterized by: –...
Page 853 RM0432 Digital filter for sigma delta modulators (DFSDM) Analog watchdog filter data for given channel y is available for reading by firmware on field WDATA[15:0] in DFSDM_CHyWDATR register. That analog watchdog filter data is converted continuously (if CHEN=1 in DFSDM_CHyCFGR1 register) with the data rate given by the analog watchdog filter setting and the channel input clock frequency.
Page 854 Digital filter for sigma delta modulators (DFSDM) RM0432 circuit event is invoked. Each input channel has its short-circuit detector. Any channel can be selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHyCFGR1 register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits, status bit SCDF[7:0], status clearing bits CLRSCDF[7:0]).
Page 855 RM0432 Digital filter for sigma delta modulators (DFSDM) CKIN Datarate samples s ⁄ ------------------------------- ...FAST = 1 ⋅ Maximum output data rate in case of parallel data input: DATAIN_RATE Datarate samples s ⁄ ------------------------------------------------------------------------------------------------------ - ...FAST = 0, Sincx filter ⋅...
Page 856 Digital filter for sigma delta modulators (DFSDM) RM0432 Signed data format in registers: Data is in a signed format in registers for final output data, analog watchdog, extremes detector, offset correction. The msb of output data word represents the sign of value (two’s complement format). 28.4.15 Launching conversions Injected conversions can be launched using the following methods:...
Page 857 RM0432 Digital filter for sigma delta modulators (DFSDM) The regular conversions executing in continuous mode can be stopped by writing ‘0’ to RCONT. After clearing RCONT, the on-going conversion is stopped immediately. In continuous mode, the data rate can be increased by setting the FAST bit in the DFSDM_FLTxCR1 register.
Page 858 Digital filter for sigma delta modulators (DFSDM) RM0432 the sequence of injected conversions finishes, the continuous regular conversions start again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular conversion result). Precedence also matters when actions are initiated by the same write to DFSDM, or if multiple actions are pending at the end of another action.
Page 859 RM0432 Digital filter for sigma delta modulators (DFSDM) – occurred when converted data (output data or data from analog watchdog filter - according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR registers – enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels AWDCH[7:0]) –...
Page 860 Digital filter for sigma delta modulators (DFSDM) RM0432 28.6 DFSDM DMA transfer To decrease the CPU intervention, conversions can be transferred into memory using a DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1 in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting bit RDMAEN=1 in DFSDM_FLTxCR1 register.
Page 861 RM0432 Digital filter for sigma delta modulators (DFSDM) Bits 23:16 CKOUTDIV[7:0]: Output serial clock divider 0: Output clock generation is disabled (CKOUT signal is set to low state) 1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 - 256 (Divider = CKOUTDIV+1).
Page 862 Digital filter for sigma delta modulators (DFSDM) RM0432 Bit 6 CKABEN: Clock absence detector enable on channel y 0: Clock absence detector disabled on channel y 1: Clock absence detector enabled on channel y Bit 5 SCDEN: Short-circuit detector enable on channel y 0: Input channel y will not be guarded by the short-circuit detector 1: Input channel y will be continuously guarded by the short-circuit detector Bit 4 Reserved, must be kept at reset value.
Page 863 RM0432 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 OFFSET[23:0]: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software. Bits 7:3 DTRBS[4:0]: Data right bit-shift for channel y 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right will be performed to have final results.
Page 864 Digital filter for sigma delta modulators (DFSDM) RM0432 Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y Bits 11:8 Reserved, must be kept at reset value.
Page 865 RM0432 Digital filter for sigma delta modulators (DFSDM) Bits 31:16 INDAT1[15:0]: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if DATMPX[1:0]=1).
Page 866 Digital filter for sigma delta modulators (DFSDM) RM0432 Bits 31:6 Reserved, must be kept at reset value. Bits 5:0 PLSSKP[5:0]: Pulses to skip for input data skipping function 0-63: Defines the number of serial input samples that will be skipped. Skipping is applied immediately after writing to this field.
Page 867 RM0432 Digital filter for sigma delta modulators (DFSDM) Bits 26:24 RCH[2:0]: Regular channel selection 0: Channel 0 is selected as the regular channel 1: Channel 1 is selected as the regular channel 7: Channel 7 is selected as the regular channel Writing these bits when RCIP=1 takes effect when the next regular conversion begins.
Page 868 Digital filter for sigma delta modulators (DFSDM) RM0432 Bits 12:8 JEXTSEL[4:0]: Trigger signal selection for launching injected conversions 0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger). This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1). Note: synchronous trigger has latency up to one f clock cycle (with deterministic jitter), DFSDMCLK asynchronous trigger has latency 2-3 f...
Page 869 RM0432 Digital filter for sigma delta modulators (DFSDM) 28.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2) Address offset: 0x104 + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. AWDCH[7:0] CKAB ROVR...
Page 870 Digital filter for sigma delta modulators (DFSDM) RM0432 Bit 2 JOVRIE: Injected data overrun interrupt enable 0: Injected data overrun interrupt is disabled 1: Injected data overrun interrupt is enabled Please see the explanation of JOVRF in DFSDM_FLTxISR. Bit 1 REOCIE: Regular end of conversion interrupt enable 0: Regular end of conversion interrupt is disabled 1: Regular end of conversion interrupt is enabled Please see the explanation of REOCF in DFSDM_FLTxISR.
Page 871 RM0432 Digital filter for sigma delta modulators (DFSDM) Bit 13 JCIP: Injected conversion in progress status 0: No request to convert the injected channel group (neither by software nor by trigger) has been issued 1: The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’...
Page 872 Digital filter for sigma delta modulators (DFSDM) RM0432 28.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) Address offset: 0x10C + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 CLRSCDF[7:0] CLRCKABF[7:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...
Page 873 RM0432 Digital filter for sigma delta modulators (DFSDM) 28.8.5 DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) Address offset: 0x110 + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res.
Page 874 Digital filter for sigma delta modulators (DFSDM) RM0432 Bits 31:29 FORD[2:0]: Sinc filter order 0: FastSinc filter type 1: Sinc filter type 2: Sinc filter type 3: Sinc filter type 4: Sinc filter type 5: Sinc filter type 6-7: Reserved –...
Page 875 RM0432 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 JDATA[23:0]: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. Bits 7:3 Reserved, must be kept at reset value.
Page 876 Digital filter for sigma delta modulators (DFSDM) RM0432 28.8.9 DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) Address offset: 0x120 + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 AWHT[23:8] AWHT[7:0] Res. Res. Res. Res. BKAWH[3:0] Bits 31:8 AWHT[23:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog.
Page 877 RM0432 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 AWLT[23:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution).
Page 878 Digital filter for sigma delta modulators (DFSDM) RM0432 28.8.12 DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) Address offset: 0x12C + 0x80 * x, (x = 0 to 3) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res.
Page 879 RM0432 Digital filter for sigma delta modulators (DFSDM) 28.8.14 DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) Address offset: 0x134 + 0x80 * x, (x = 0 to 3) Reset value: 0x7FFF FF00 EXMIN[23:8] rc_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r...
Page 880 Digital filter for sigma delta modulators (DFSDM) RM0432 Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / f DFSDMCLK The timer has an input clock from DFSDM clock (system clock ). Conversion time DFSDMCLK measurement is started on each conversion start and stopped when conversion finishes (interval between first and last serial sample).
Page 881 RM0432 Digital filter for sigma delta modulators (DFSDM) Table 191. DFSDM register map and reset values (continued) Register Offset name DFSDM_ CH1CFGR1 0x20 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH1CFGR2 0x24 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH1AWSCDR 0x28 reset value DFSDM_ WDATA[15:0] CH1WDATR...
Page 882 Digital filter for sigma delta modulators (DFSDM) RM0432 Table 191. DFSDM register map and reset values (continued) Register Offset name DFSDM_ CH3CFGR1 0x60 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH3CFGR2 0x64 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH3AWSCDR 0x68 reset value DFSDM_ WDATA[15:0] CH3WDATR...
Page 883 RM0432 Digital filter for sigma delta modulators (DFSDM) Table 191. DFSDM register map and reset values (continued) Register Offset name DFSDM_ CH5CFGR1 0xA0 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH5CFGR2 0xA4 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH5AWSCDR 0xA8 reset value DFSDM_ WDATA[15:0] CH5WDATR...
Page 884 Digital filter for sigma delta modulators (DFSDM) RM0432 Table 191. DFSDM register map and reset values (continued) Register Offset name DFSDM_ CH7CFGR1 0xE0 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CH7CFGR2 0xE4 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] CH7AWSCDR 0xE8 reset value DFSDM_ WDATA[15:0] CH7WDATR...
Page 885 RM0432 Digital filter for sigma delta modulators (DFSDM) Table 191. DFSDM register map and reset values (continued) Register Offset name DFSDM_ JDATA[23:0] FLT0JDATAR 0x118 reset value RDATA DFSDM_ RDATA[23:0] CH[2:0] FLT0RDATAR 0x11C reset value DFSDM_ AWHT[23:0] BKAWH[3:0] FLT0AWHTR 0x120 reset value DFSDM_ AWLT[23:0] BKAWL[3:0]...
Page 886 Digital filter for sigma delta modulators (DFSDM) RM0432 Table 191. DFSDM register map and reset values (continued) Register Offset name DFSDM_ FLT1ICR 0x18C reset value DFSDM_ JCHG[7:0] FLT1JCHGR 0x190 reset value DFSDM_ FOSR[9:0] IOSR[7:0] FLT1FCR 0x194 reset value DFSDM_ JDATA[23:0] FLT1JDATAR 0x198 reset value...
Page 887 RM0432 Digital filter for sigma delta modulators (DFSDM) Table 191. DFSDM register map and reset values (continued) Register Offset name DFSDM_ RCH[2:0] JEXTSEL[4:0] FLT2CR1 0x200 reset value DFSDM_ AWDCH[7:0] EXCH[7:0] FLT2CR2 0x204 reset value DFSDM_ FLT2ISR 0x208 reset value DFSDM_ FLT2ICR 0x20C reset value...
Page 888 Digital filter for sigma delta modulators (DFSDM) RM0432 Table 191. DFSDM register map and reset values (continued) Register Offset name DFSDM_ EXMAX[23:0] FLT2EXMAX 0x230 reset value DFSDM_ EXMIN[23:0] FLT2EXMIN 0x234 reset value DFSDM_ CNVCNT[27:0] FLT2CNVTIMR 0x238 reset value 0x23C - Reserved 0x27C DFSDM_...
Page 889 RM0432 Digital filter for sigma delta modulators (DFSDM) Table 191. DFSDM register map and reset values (continued) Register Offset name RDATA DFSDM_ RDATA[23:0] CH[2:0] FLT3RDATAR 0x29C reset value DFSDM_ AWHT[23:0] BKAWH[3:0] FLT3AWHTR 0x2A0 reset value DFSDM_ AWLT[23:0] BKAWL[3:0] FLT3AWLTR 0x2A4 reset value DFSDM_ AWHTF[7:0]...
Page 890 LCD-TFT display controller (LTDC) RM0432 LCD-TFT display controller (LTDC) 29.1 Introduction The LCD-TFT (liquid crystal display - thin film transistor) display controller provides a parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD and TFT panels.
Page 891 RM0432 LCD-TFT display controller (LTDC) 29.4 LTDC functional description 29.4.1 LTDC block diagram The block diagram of the LTDC is shown in the figure below. Figure 199. LTDC block diagram Pixel clock domain Layer1 LCD_HSYNC FIFO LCD_VSYNC Dithering Blending unit interface unit LCD_DE...
Page 892 LCD-TFT display controller (LTDC) RM0432 The LTDC-TFT controller pins must be configured by the user application. The unused pins can be used for other purposes. For LTDC outputs up to 24 bits (RGB888), if less than 8 bpp are used to output for example RGB565 or RGB666 to interface on 16- or 18-bit displays, the RGB display data lines must be connected to the MSB of the LCD-TFT controller RGB data lines.
Page 893 RM0432 LCD-TFT display controller (LTDC) Table 194. Clock domain for each register (continued) LTDC register Clock domain LTDC_SSCR LTDC_BPCR LTDC_AWCR LTDC_TWCR LTDC_GCR LTDC_BCCR LTDC_LIPCR LTDC_CPSR LTDC_CDSR Pixel clock (LCD_CLK) LTDC_LxWHPCR LTDC_LxWVPCR LTDC_LxCKCR LTDC_LxPFCR LTDC_LxCACR LTDC_LxDCCR LTDC_LxBFCR LTDC_LxCLUTWR Care must be taken while accessing the LTDC registers, the APB2 bus is stalled during: •...
Page 894 LCD-TFT display controller (LTDC) RM0432 horizontal and vertical synchronization timings panel signals, the pixel clock and the data enable signals. Figure 200. LCD-TFT synchronous timings Total width Active width VSYNC width Data1, Line1 Active display area Active height Data(n), Line(n) MSv19674V1 Note: The HBP and HFP are respectively the horizontal back porch and front porch period.
Page 895 RM0432 LCD-TFT display controller (LTDC) Note: When the LTDC is enabled, the timings generated start with X/Y=0/0 position as the first horizontal synchronization pixel in the vertical synchronization area and following the back porch, active data display area and the front porch. When the LTDC is disabled, the timing generator block is reset to X = total width - 1, Y = total height - 1 and held the last pixel before the vertical synchronization phase and the FIFO are flushed.
Page 896 LCD-TFT display controller (LTDC) RM0432 The dithering can be switched on and off on the fly through the LTDC_GCR register. Reload shadow registers Some configuration registers are shadowed. The shadow registers values can be reloaded immediately to the active registers when writing to these registers or at the beginning of the vertical blanking period following the configuration in the LTDC_SRCR register.
Page 897 RM0432 LCD-TFT display controller (LTDC) The programmable layer position and size defines the first/last visible pixel of a line and the first/last visible line in the window. It allows to display either the full image frame or only a part of the image frame (see the figure below): •...
Page 898 LCD-TFT display controller (LTDC) RM0432 Table 195. Pixel data mapping versus color format (continued) [7:0] [7:0] [7:0] [7:0] RGB565 [4:0] G [5:3] [2:0] B [4:0] [4:0] G [5:3] [2:0] B [4:0] [4:0] G [5:3] [2:0] B [4:0] [4:0] G [5:3] [2:0] B [4:0] ARGB1555...
Page 899 RM0432 LCD-TFT display controller (LTDC) Color look-up table (CLUT) The CLUT can be enabled at run-time for every layer through the LTDC_LxCR register and it is only useful in case of indexed color when using the L8, AL44 and AL88 input pixel format.
Page 900 LCD-TFT display controller (LTDC) RM0432 Layer blending The blending is always active and the two layers can be blended following the blending factors configured through the LTDC_LxBFCR register. The blending order is fixed and it is bottom up. If two layers are enabled, first the Layer1 is blended with the Background color, then the layer2 is blended with the result of blended color of layer1 and the background.
Page 901 RM0432 LCD-TFT display controller (LTDC) 29.6 LTDC interrupts The LTDC provides four maskable interrupts logically ORed to two interrupt vectors. The interrupt sources can be enabled or disabled separately through the LTDC_IER register. Setting the appropriate mask bit to 1 enables the corresponding interrupt. The two interrupts are generated on the following events: •...
Page 902 LCD-TFT display controller (LTDC) RM0432 29.7 LTDC programming procedure The steps listed below are needed to program the LTDC: Enable the LTDC clock in the RCC register. Configure the required pixel clock following the panel datasheet. Configure the synchronous timings: VSYNC, HSYNC, vertical and horizontal back porch, active data area and the front porch timings following the panel datasheet as described in the Section 29.5.1: LTDC global configuration...
Page 903 RM0432 LCD-TFT display controller (LTDC) 29.8 LTDC registers 29.8.1 LTDC synchronization size configuration register (LTDC_SSCR) This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure 200 Section 29.5: LTDC programmable parameters for an example of configuration.
Page 904 LCD-TFT display controller (LTDC) RM0432 Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 AHBP[11:0]: accumulated horizontal back porch (in units of pixel clock period) These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1.
Page 905 RM0432 LCD-TFT display controller (LTDC) 29.8.4 LTDC total width configuration register (LTDC_TWCR) This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNC width + HBP + active width + HFP - 1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNC height + BVBP + active height + VFP - 1).
Page 906 LCD-TFT display controller (LTDC) RM0432 Bit 31 HSPOL: horizontal synchronization polarity This bit is set and cleared by software. 0: horizontal synchronization polarity is active low. 1: horizontal synchronization polarity is active high. Bit 30 VSPOL: vertical synchronization polarity This bit is set and cleared by software. 0: vertical synchronization is active low.
Page 907 RM0432 LCD-TFT display controller (LTDC) 29.8.6 LTDC shadow reload configuration register (LTDC_SRCR) This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.
Page 908 LCD-TFT display controller (LTDC) RM0432 Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 BCRED[7:0]: background color red value These bits configure the background red value. Bits 15:8 BCGREEN[7:0]: background color green value These bits configure the background green value. Bits 7:0 BCBLUE[7:0]: background color blue value These bits configure the background blue value.
Page 909 RM0432 LCD-TFT display controller (LTDC) 29.8.9 LTDC interrupt status register (LTDC_ISR) This register returns the interrupt status flag. Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 910 LCD-TFT display controller (LTDC) RM0432 Bits 31:4 Reserved, must be kept at reset value. Bit 3 CRRIF: clears register reload interrupt flag 0: no effect 1: clears the RRIF flag in the LTDC_ISR register Bit 2 CTERRIF: clears the transfer error interrupt flag 0: no effect 1: clears the TERRIF flag in the LTDC_ISR register.
Page 911 RM0432 LCD-TFT display controller (LTDC) Bits 31:16 CXPOS[15:0]: current X position These bits return the current X position. Bits 15:0 CYPOS[15:0]: current Y position These bits return the current Y position. 29.8.13 LTDC current display status register (LTDC_CDSR) This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals.
Page 912 LCD-TFT display controller (LTDC) RM0432 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLUTEN Res. Res. COLKEN Bits 31:5 Reserved, must be kept at reset value. Bit 4 CLUTEN: color look-up table enable This bit is set and cleared by software.
Page 913 RM0432 LCD-TFT display controller (LTDC) Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 WHSPPOS[11:0]: window horizontal stop position These bits configure the last visible pixel of a line of the layer window. WHSPPOS[11:0] must be ≥ AHBP[11:0] bits + 1 (programmed in LTDC_BPCR register). Bits 15:12 Reserved, must be kept at reset value.
Page 914 LCD-TFT display controller (LTDC) RM0432 Example: The LTDC_BPCR register is configured to 0x000E0005 (AVBP[10:0] is 0x5) and the LTDC_AWCR register is configured to 0x028E01E5 (AAH[10:0] is 0x1E5). To configure the vertical position of a window size of 630x460, with vertical start offset of 8 lines in the active data area: layer window first line: WVSTPOS[10:0] must be programmed to 0xE (0x5 + 1 + 0x8).
Page 915 RM0432 LCD-TFT display controller (LTDC) Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PF[2:0]: pixel format These bits configure the pixel format 000: ARGB8888 001: RGB888 010: RGB565 011: ARGB1555 100: ARGB4444 101: L8 (8-bit luminance) 110: AL44 (4-bit alpha, 4-bit luminance) 111: AL88 (8-bit alpha, 8-bit luminance) 29.8.19 LTDC layer x constant alpha configuration register...
Page 916 LCD-TFT display controller (LTDC) RM0432 29.8.20 LTDC layer x default color configuration register (LTDC_LxDCCR) This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.
Page 917 RM0432 LCD-TFT display controller (LTDC) 29.8.21 LTDC layer x blending factors configuration register (LTDC_LxBFCR) This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs • BC = blended color •...
Page 918 LCD-TFT display controller (LTDC) RM0432 Note: The constant alpha value, is the programmed value in the LxCACR register divided by 255 by hardware. Example: Only layer1 is enabled, BF1 configured to constant alpha. BF2 configured to constant alpha. The constant alpha programmed in the LxCACR register is 240 (0xF0). Thus, the constant alpha value is 240/255 = 0.94.
Page 919 RM0432 LCD-TFT display controller (LTDC) Bits 12:0 CFBLL[12:0]: color frame buffer line length These bits define the length of one line of pixels in bytes + 3. The line length is computed as follows: active high width * number of bytes per pixel + 3. Example: •...
Page 920 LCD-TFT display controller (LTDC) RM0432 29.8.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR) This register defines the CLUT address and the RGB value. Address offset: 0xC4 + 0x80 * (x - 1), (x = 1 to 2) Reset value: 0x0000 0000 CLUTADD[7:0] RED[7:0] GREEN[7:0]...
Page 921 RM0432 LCD-TFT display controller (LTDC) 29.8.26 LTDC register map The following table summarizes the LTDC registers. Table 197. LTDC register map and reset values Offset Register name LTDC_SSCR HSW[11:0] VSH[10:0] 0x0008 Reset value LTDC_BPCR AHBP[11:0] AVBP[10:0] 0x000C Reset value LTDC_AWCR AAW[11:0] AAH[10:0] 0x0010...
Page 922 LCD-TFT display controller (LTDC) RM0432 Table 197. LTDC register map and reset values (continued) Offset Register name LTDC_L1CR 0x0084 Reset value LTDC_L1WHPCR WHSPPOS[11:0] WHSTPOS[11:0] 0x0088 Reset value LTDC_L1WVPCR WVSPPOS[10:0] WVSTPOS[10:0] 0x008C Reset value LTDC_L1CKCR CKRED[7:0] CKGREEN[7:0] CKBLUE[7:0] 0x0090 Reset value LTDC_L1PFCR PF[2:0] 0x0094...
Page 923 RM0432 LCD-TFT display controller (LTDC) Table 197. LTDC register map and reset values (continued) Offset Register name LTDC_L2WVPCR WVSPPOS[10:0] WVSTPOS[10:0] 0x010C Reset value LTDC_L2CKCR CKRED[7:0] CKGREEN[7:0] CKBLUE[7:0] 0x0110 Reset value LTDC_L2PFCR PF[2:0] 0x0114 Reset value LTDC_L2CACR CONSTA[7:0] 0x0118 Reset value LTDC_L2DCCR DCALPHA[7:0] DCRED[7:0]...
Page 924 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.1 Introduction The Display Serial Interface (DSI) is part of a group of communication protocols defined by ® ® the MIPI Alliance.
Page 925 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.3 DSI Host main features ® • Compliant with MIPI Alliance standards (see Section 30.2: Standard and references) ® • Interface with MIPI D-PHY ® • Supports all commands defined in the MIPI Alliance specification for DCS: –...
Page 926 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.4 DSI Host functional description 30.4.1 General description ® The MIPI DSI Host includes dedicated video interfaces internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display. More in detail: •...
Page 927 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only standard procedure to estimate the minimum lane rate and the minimum number of lanes that support a specific display device. The basic assumptions for estimates are: • clock lane frequency is 250 MHz, resulting in a bandwidth of 500 Mbps for each data lane;...
Page 928 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 a High-Speed transmission. It also performs data splitting between available D-PHY lanes for High-Speed transmission. • The Packet Handler schedules the activities inside the link. It performs several functions based on the interfaces that are currently operational and the video transmission mode that is used (burst mode or non-burst mode with sync pulses or sync events).
Page 929 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.5 Functional description: Video mode on LTDC interface The LTDC interface captures the data and control signals and conveys them to the FIFO interfaces that transmit them to the DSI link. Two different streams of data are present at the interface, namely video control signals and pixel data.
Page 930 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 The LTDC interface can be configured to increase flexibility and promote correct use of this interface for several systems. The following configuration options are available: • Polarity control: All the control signals are programmable to change the polarity depending on the LTDC configuration.
Page 931 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Burst mode In this mode, the entire active pixel line is buffered into a FIFO and transmitted in a single packet with no interruptions. This transmission mode requires that the DPI Pixel FIFO has the capacity to store a full line of active pixel data inside it.
Page 932 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 When the null packets are enabled: lanebyteclkperiod * NUMC (VPSIZE * bytes_per_pixel + 12 + NPSIZE) / number_of_lanes = pixels_per_line * LTDC_Clock_period When the null packets are disabled: lanebyteclkperiod * NUMC (VPSIZE * bytes_per_pixel + 6) / number_of_lanes = pixels_per_line * LTDC_Clock_period 30.5.2 Updating the LTDC interface configuration in video mode...
Page 933 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only In situations when it is required to immediately update the active registers without the reset (as illustrated in Figure 207), ensure that the Enable (EN) and Update Register (UR) bits of the DSI Host Video Shadow Control Register (DSI_VSCR) are set to 0.
Page 934 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.6 Functional description: adapted command mode on LTDC interface The Adapted Command mode, enables the system to input a stream of pixel from the LTDC that is conveyed by DSI Host using the Command mode transmission (using the DCS packets).
Page 935 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Figure 209. Adapted command mode usage flow Video engine DSI controller Display MSv35860V1 When the Command mode (CMDM) bit of the DSI Host mode Configuration Register (DSI_CFGR) is set to 1, the LTDC interface assume the behavior corresponding to the Adapted Command mode.
Page 936 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 when the last pixel of the image is received falls or Command Size (CMDSIZE) limit is reached. Synchronization with the LTDC The DSI wrapper performs the synchronization of the transfer process by : •...
Page 937 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only If the Tearing Effect Interrupt Enable (TEIE) bit of the DSI Wrapper Interrupt Enable Register (DSI_WIER) is set, an interrupt is generated. Tearing effect through DSI link When the TESRC bit of the DSI Wrapper Configuration Register (DSI_WCFGR) is reset, the Tearing effect is managed through the DSI link: The DSI Host performs a double Bus-Turn-Around (BTA) after sending the set_tear_on command granting the ownership of the link to the DSI display.
Page 938 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.7 Functional description: APB slave generic interface The APB slave interface allows the transmission of generic information in Command mode, and follows a proprietary register interface. Commands sent through this interface are not constrained to comply with the DCS specification, and can include generic commands described in the DSI specification as manufacturer-specific.
Page 939 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.7.1 Packet transmission using the generic interface The transfer of packets through the APB bus is based on the following conditions: • The APB protocol defines that the write and read procedure takes two clock cycles each to be executed.
Page 940 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Figure 210. 24 bpp APB pixel to byte organization [31 …………………. 0] 8 bit 8 bit 8 bit 8 bit Write_mem pwdata(0) B0[7:0] G0[7:0] R0[7:0] Command Pixel 24 bpp pwdata(1) R2[7:0] B1[7:0] G1[7:0]...
Page 941 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Figure 212. 16 bpp APB pixel to byte organization [31 …………………. 0] 8 bit 8 bit 8 bit 8 bit Write_mem pwdata(0) G0[2:0] B0[4:0] R0[4:0] G0[5:3] R1[4:0] G1[5:3] Pixel Command 16 bpp pwdata(1) R3[4:0]...
Page 942 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.8 Functional description: Timeout counters The DSI Host includes counters to manage timeout during the various communication phases. The duration of each timeout can be configured by the 6 DSI Host Timeout Counter Configuration Register (DSI_TCCR0..5).
Page 943 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only If that counter reaches the value defined by the Low-Power Reception Timeout Counter (LPRX_TOCNT) field of the DSI Host Timeout Counter Configuration Register 1 (DSI_TCCR0), the Timeout Low-Power Reception (TOLPRX) bit in the DSI Host Interrupt and Status Register 1 (DSI_ISR1) is asserted and an internal soft reset is generated to the DSI Host.
Page 944 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Figure 215. Timing of PRESP_TO after a bus turn-around Host Device LP-11 Device Ready MSv35866V1 944/2301 RM0432 Rev 6...
Page 945 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Figure 216. Timing of PRESP_TO after a Read Request (HS or LP) Host Device LP-11 Device Ready MSv35867V1 RM0432 Rev 6 945/2301 1044...
Page 946 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Figure 217. Timing of PRESP_TO after a Write Request (HS or LP) Host Device LP-11 Device Ready MSv35868V1 Table 202 describes the fields used for the configuration of the PRESP_TO counter. Table 202.
Page 947 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only mode for High-Speed write operation timeout. When set to 1, this bit allows the PRESP_TO from HSWR_TOCNT to be used only once, when both of the following conditions are met: •...
Page 948 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.9 Functional description: transmission of commands 30.9.1 Transmission of commands in Video mode The DSI Host supports the transmission of commands, both in High-Speed and Low-Power, while in Video mode. The DSI Host uses Blanking or Low-Power (BLLP) periods to transmit commands inserted through the APB Generic interface.
Page 949 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Figure 220. Transmission of commands on the last line of a frame Where vsync would have asserted if dpihalt stayed low frame time frame time dpivsync dpihsync dpidataen edpihalt vsync can assert immediately after dpihalt de-asserts MSv35881V1 Only one command is transmitted per line, even in the case of the last line of a frame but...
Page 950 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.9.2 Transmission of commands in Low-power mode DSI Host can be configured to send the Low-Power commands during the High-Speed Video mode transmission. To enable this feature, set the Low Power Command Enable (LPCE) bit of the DSI Host Video mode Configuration Register (DSI_VMCR) to 1.
Page 951 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Figure 222. LPSIZE for Burst or Non-Burst with sync events HS -> LP LPDT LPDT LPS -> HS HSÆLP outvact_lpcmd_time LPÆHS MSv35871V1 This time is calculated as follows: LPSIZE = (t - (t + 2 t )) / (2 ×...
Page 952 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 In this example, a 13-byte command can be transmitted as follows: LPSIZE = (12.4 μs - (420 ns + 180 ns +200 ns + (22 × 50 ns + 2 × 50 ns))) / (2 × 8 × 50 ns) = 13 bytes.
Page 953 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only where • = line time; • = time of the HSA pulse (DSI_VHSACR.HSA); • = time of Horizontal back porch (DSI_VHBPCR.HBP); • = time of Video active. For Burst mode, the Video active is time compressed and HACT is calculated as t = VPSIZE * Bytes_per_Pixel /Number_Lanes * t...
Page 954 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Figure 226 illustrates the meaning of VLPSIZE and LPSIZE, matching them with the shaded areas and the VACT region. Figure 226. Location of LPSIZE and VLPSIZE in the image area VSA and BLLP VBP lines...
Page 955 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only MRD_TIME = (t + 2 x t ) / lanebyteclkperiod, where: HS->LP LP->HS LPDT lprd read • = Time to enter the Low-Power mode; HS->LP • = Time to leave the Low-Power mode; LP->HS •...
Page 956 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 The DSI Host decides the best approach to follow regarding power saving out of the three possible scenarios: • there is no enough time to go to the Low-Power mode. Therefore, blanking period is added as shown in Figure 227;...
Page 957 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.10 Functional description: virtual channels The DSI Host supports choosing the Virtual Channel (VC) for use for each interface. Using multiple Virtual Channels, the system can address multiples displays at the same time, when each display has a different Virtual Channel identifier.
Page 958 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.11 Functional description: video mode pattern generator The Video mode pattern generator allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any stimuli. The frame requirements must be defined in video registers that are listed in Table 203.
Page 959 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Figure 231. Vertical color bar mode Figure 232. Horizontal color bar mode 30.11.2 Color coding Table 204 shows the RGB components used. RM0432 Rev 6 959/2301 1044...
Page 960 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Table 204. RGB components White Yellow Cyan Green Magenta Blue Black High High High High High High High High High High High High 30.11.3 BER testing pattern The BER testing pattern simplifies conformance testing. This pattern tests the RX D-PHY capability to receive the data correctly.
Page 961 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.11.4 Video mode pattern generator resolution Depending on the orientation, BER mode, and color coding, the smallest resolutions accepted by the Video mode pattern generator are: • BER mode: 8x8; •...
Page 962 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.12 Functional description: D-PHY management ® The embedded MIPI D-PHY is control directly by the DSI Host and is configured through the DSI Wrapper. A dedicated PLL and a dedicated 1.2 V regulator are also embedded to supply the clock and the power supply to the DSI Host and D-PHY.
Page 963 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Special Sdd Control An additional current path can be activated on both clock lane and data lane to meet the ® parameter defined in the MIPI D-PHY Specification. This activation is done setting the SDDC bit of the DSI_WPCR1 register. Custom lane configuration To ease DSI integration, lane pins can be swapped and/or High-Speed signal can be inverted on a lane as described in...
Page 964 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.12.2 Special D-PHY operations The DSI Wrapper have some control bit to force the D-PHY in some particular state and/or behavior. Forcing lane state It’s possible to force the data lane and/or the clock lane in TX Stop mode through the bits FTXSMDL and FTXSMCL of the DSI_WPCR1 register.
Page 965 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.12.4 DSI PLL control The dedicated DSI PLL is controlled through the DSI Wrapper, as shown in Figure 236 (analog blocks and signals in pink, digital signals in black, digital blocks in light blue). Figure 236.
Page 966 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 If the PLL gets unlocked, the PLLUIF bit of the DSI_WISR is set. If the PLLUIE bit of the DSI_WIER register is set, an interrupt is generated. The DSI PLL setting can be changed only when the PLL is disabled. 30.12.5 Regulator control The DSI regulator providing the 1.2 V is controlled through the DSI Wrapper.
Page 967 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.13 Functional description: interrupts and errors The interrupts can be generated either by the DSI Host or by the DSI Wrapper. All the interrupts are merged in one interrupt lane going to the Interrupt Controller. 30.13.1 DSI wrapper interrupts An interrupt can be produced on the following events:...
Page 968 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 The light yellow boxes in Figure 237 illustrate the location of some of the errors. Figure 237. Error sources DPI_PAYLOAD_WR_ERR Packet Handler LTDC ctrl FIFO LTDC LTDC Video Mode FSM Interface LTDC pixel FIFO...
Page 969 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Table 209. Error causes and recovery (continued) DSI host interrupt Recommended method Name Cause of the error & Status register of handling the error Device does not behave as expected, The D-PHY reports the False communication with the Device is not Control Error.
Page 970 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Table 209. Error causes and recovery (continued) DSI host interrupt Recommended method Name Cause of the error & Status register of handling the error The Acknowledge with Error Check the Device capabilities. It is possible packet contains this error.
Page 971 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Table 209. Error causes and recovery (continued) DSI host interrupt Recommended method Name Cause of the error & Status register of handling the error It is possible that the Host and Device timeout counters are not correctly configured.
Page 972 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Table 209. Error causes and recovery (continued) DSI host interrupt Recommended method Name Cause of the error & Status register of handling the error The Read FIFO size is not correctly dimensioned for the maximum read-back packet size.
Page 973 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Table 209. Error causes and recovery (continued) DSI host interrupt Recommended method Name Cause of the error & Status register of handling the error The integrity of the received data cannot be Host receives a transmission guaranteed.
Page 974 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.14 Programing procedure ® To operate DSI Host, you must be familiar with the MIPI DSI specification. Every software programmable register is accessible through the APB interface. 30.14.1 Programing procedure overview The programming procedure for Video mode or Adapted Command mode must respect the following order: Configure the RCC (refer to the RCC chapter)
Page 975 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Configuring the D-PHY parameters in the DSI wrapper The DSI wrapper can be used to fine tunes either timing or physical parameters of the D- PHY. This operation is not required for a standard usage of the D-PHY. All the fields and parameters are described in the register description of the DSI wrapper.
Page 976 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.14.4 Configuring flow control and DBI interface The flow control is configured thanks to the DSI Host Protocol Configuration Register (DSI_PCR). The configuration parameters are the following • CRC Reception Enable (CRCRXE bit) •...
Page 977 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.14.6 Configuring the video mode The video mode configuration shall defines the behavior of the controller in Low-power for command transmission, the type of video transmission (burst or non-burst mode) and the panel horizontal and vertical timing: •...
Page 978 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 line, a malfunction occurs. This phenomenon can be avoided by configuring the DSI Host to go to Low-Power once per line. – Configure the horizontal sync duration (DSI_VHSACR.HSA) with the time taken by a LTDC Horizontal Sync Active period measured in cycles of lane byte clock (normally a period of 8 ns).
Page 979 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Figure 238. Video packet transmission configuration flow diagram Global configuration Configure the DPI I/F Burst Mode Determine the Configure DSI link to pixel ratio video_packet_size Enable If the DSI link to multiple packets pixel ratio is >1 Determine number of pixel per packet...
Page 980 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Configuration steps: • Video transmission mode configuration: Configure the Low-Power transitions: DSI_VMCR[13:8] = 6'b111111, to enable LP in all video period. DSI_VMCR.FBTAAE = 1, for the DSI Host to request an acknowledge response message from the peripheral at the end of each frame.
Page 981 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.14.8 Configuring the video mode pattern generator DSI Host can transmit a color bar pattern without horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli. Figure 239 shows the programming sequence to send a test pattern: Configure the DSI_MCR register to enable video mode.
Page 982 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Figure 240. Frame configuration registers DSI_VVSACR.VSA (Line) DSI_VVBPCR.VBP (Line) DSI_VHSACR.HSA DSI_VHBPCR.HBP DSI_VPCR.VPSIZE (Pixel) * DSI_VCCR.NUMC (lanebyteclk) (lanebyteclk) (lanebyteclk) DSI_VVFPCR.VFP (Line) DSI_VLCR.HLINE (lanebyteclk) MSv35877V1 Note: The number of pixels of payload is restricted to a multiple of a value provided in Table 199.
Page 983 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.14.9 Managing ULPM There are two ways to configure the software to enter and exit the ULPM: • Enter and Exit the ULPM with the D-PHY PLL running. This is a faster process. •...
Page 984 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Process flow to exit the ULPM Implement the process flow described in the following procedure to exit the ULPM on both clock lane and data lanes: Verify that all active lanes are in ULPM: –...
Page 985 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.15 DSI Host registers 30.15.1 DSI Host Version Register (DSI_VR) Address offset: 0x0000 Reset value: 0x3133 302A VERSION[31:16] VERSION[15:0] Bits 31: 0 VERSION: Version of the DSI Host This RO register contains the version of the DSI Host 30.15.2 DSI Host Control Register (DSI_CR) Address offset: 0x0004...
Page 986 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.15.3 DSI HOST Clock Control Register (DSI_CCR) Address offset: 0x0008 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TOCKDIV[7:0] TXECKDIV[7:0] Bits 31: 16 Reserved, must be kept at reset value...
Page 987 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.15.5 DSI Host LTDC Color Coding Register (DSI_LCOLCR) Address offset: 0x0010 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 988 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Bit 1 VSP: VSYNC Polarity This bit configures the polarity of VSYNC pin. 0: Shutdown pin active high (default). 1: Shutdown pin active low. Bit 0 DEP: Data Enable Polarity This bit configures the polarity of Data Enable pin.
Page 989 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Bits 31: 5 Reserved, must be kept at reset value Bit 4 CRCRXE: CRC Reception Enable This bit enables the CRC reception and error reporting. 0: CRC reception is disabled. 1: CRC reception is enabled.
Page 990 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.15.10 DSI Host mode Configuration Register (DSI_MCR) Address offset: 0x0034 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 991 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Bit 16 PGE: Pattern Generator Enable This bit enables the video mode pattern generator. 0: Pattern generator is disabled. 1: Pattern generator is enabled. Bit 15 LPCE: Low-Power Command Enable This bit enables the command transmission only in Low-Power mode.
Page 992 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Bit 8 LPVSAE: Low-Power Vertical Sync Active Enable This bit enables to return to Low-Power inside the Vertical Sync time (VSA) period when timing allows. 0: Return to Low-Power inside the VSA is disabled. 1: Return to Low-Power inside the VSA is enabled Bits 7: 2 Reserved, must be kept at reset value Bits 1: 0 VMT: video mode Type...
Page 993 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Bits 31: 13 Reserved, must be kept at reset value Bits 12: 0 NUMC: Number of Chunks This register configures the number of chunks to be transmitted during a Line period (a chunk consists of a video packet and a null packet).
Page 994 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.15.16 DSI Host Video HBP Configuration Register (DSI_VHBPCR) Address offset: 0x004C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 995 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only Bits 31: 10 Reserved, must be kept at reset value Bits 9: 0 VSA: Vertical Synchronism Active duration This fields configures the Vertical Synchronism Active period measured in number of horizontal lines.
Page 996 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.15.21 DSI Host Video VA Configuration Register (DSI_VVACR) Address offset: 0x0060 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 997 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.15.23 DSI Host Command mode Configuration Register (DSI_CMCR) Address offset: 0x0068 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. MRDPS Res. Res. Res. Res. DLWTX DSR0TX DSW1TX DSW0TX Res.
Page 998 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 Bit 13 GSR2TX: Generic Short Read Two parameters Transmission This bit configures the Generic short read packet with two parameters command transmission type: 0: High-speed. 1: Low-power. Bit 12 GSR1TX: Generic Short Read One parameters Transmission This bit configures the Generic short read packet with one parameters command transmission type: 0: High-speed.
Page 999 RM0432 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only 30.15.24 DSI Host Generic Header Configuration Register (DSI_GHCR) Address offset: 0x006C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. WCMSB[7:0] WCLSB[7:0] VCID[1:0] DT[5:0] Bits 31: 24 Reserved, must be kept at reset value Bits 23: 16 WCMSB: WordCount MSB This field configures the most significant byte of the header packet’s word count for long packets or data 1 for short packet.
Page 1000 DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only RM0432 30.15.26 DSI Host Generic Packet Status Register (DSI_GPSR) Address offset: 0x0074 Reset value: 0x0000 0015 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.